Semiconductor device

• US 10,424,582 B2
• Filed: 07/03/2018
• Issued: 09/24/2019
• Est. Priority Date: 02/19/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Saito, Toshihiko
• Primary Examiner(s): Tran, Tan N
• Application Number:
  US16/026,530
• Publication Number:
  US 20190013318A1
• Time in Patent Office: 448 Days
• Field of Search: 257 59, 257 82, 257432, 257 72
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/247 Amorphous materials
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

At least one of a plurality of transistors which are highly integrated in an element is provided with a back gate without increasing the number of manufacturing steps. In an element including a plurality of transistors which are longitudinally stacked, at least a transistor in an upper portion includes a metal oxide having semiconductor characteristics, a same layer as a gate electrode of a transistor in a lower portion is provided to overlap with a channel formation region of the transistor in an upper portion, and part of the same layer as the gate electrode functions as a back gate of the transistor in an upper portion. The transistor in a lower portion which is covered with an insulating layer is subjected to planarization treatment, whereby the gate electrode is exposed and connected to a layer functioning as source and drain electrodes of the transistor in an upper portion.

Claims

1. A semiconductor device comprising a circuit, the circuit comprising:

a first transistor comprising;

a first semiconductor layer;

a first gate insulating layer over the first semiconductor layer; and

a first gate electrode over the first gate insulating layer;

an insulating layer over the first semiconductor layer;

a second transistor comprising;

a second gate electrode;

a second gate insulating layer over the second gate electrode, the second gate insulating layer comprising part of the insulating layer;

a second semiconductor layer over the second gate insulating layer; and

a third gate electrode over the second semiconductor layer;

a capacitor comprising;

a first electrode; and

a second electrode over the first electrode,

wherein the first semiconductor layer comprises silicon,

wherein the second semiconductor layer comprises an oxide semiconductor,

wherein the first electrode comprises silicon,

wherein the second gate electrode is over and in contact with the first gate insulating layer,

wherein the second electrode is electrically connected to the first gate electrode, and

wherein the first gate electrode is electrically connected to one of a source and a drain of the second transistor.

2. The semiconductor device according to claim 1, wherein the first transistor is formed using an SOI substrate.

3. The semiconductor device according to claim 1, wherein the first transistor is formed using a silicon substrate.

4. The semiconductor device according to claim 1, wherein the insulating layer has a leveled upper surface.

5. The semiconductor device according to claim 1, wherein a top surface of the first gate electrode is not covered by the insulating layer.

6. The semiconductor device according to claim 1, wherein the circuit is a memory element.

7. The semiconductor device according to claim 1, wherein the second gate electrode is formed from a same layer as the first gate electrode.

8. A semiconductor device comprising a circuit, the circuit comprising:

a first transistor comprising;

a first gate electrode;

a first gate insulating layer over the first gate electrode;

a first semiconductor layer;

a second gate insulating layer over the first semiconductor layer; and

a second gate electrode over the second gate insulating layer;

an insulating layer over the first semiconductor layer;

a second transistor comprising;

a third gate electrode;

a third gate insulating layer over the third gate electrode, the third gate insulating layer comprising part of the insulating layer; and

a second semiconductor layer over the third gate insulating layer,

wherein the insulating layer is between the second semiconductor layer and the third gate electrode,

wherein the second semiconductor layer comprises an oxide semiconductor,

wherein the third gate electrode is over and in contact with the second gate insulating layer, and

wherein the second gate electrode is electrically connected to one of a source and a drain of the second transistor.

9. The semiconductor device according to claim 8, wherein the first transistor is formed using a silicon substrate.

10. The semiconductor device according to claim 8, wherein the insulating layer has a leveled upper surface.

11. The semiconductor device according to claim 8, wherein a top surface of the first gate electrode is not covered by the insulating layer.

12. The semiconductor device according to claim 8, wherein the circuit is a memory element.

13. The semiconductor device according to claim 8, wherein the third gate electrode is formed from a same layer as the second gate electrode.

14. A semiconductor device comprising a circuit, the circuit comprising:

a first transistor comprising;

a first gate electrode;

a first gate insulating layer over the first gate electrode;

a first semiconductor layer;

a second gate insulating layer over the first semiconductor layer; and

a second gate electrode over the second gate insulating layer;

an insulating layer over the first semiconductor layer;

a second transistor comprising;

a third gate electrode;

a third gate insulating layer over the third gate electrode, the third gate insulating layer comprising part of the insulating layer; and

a second semiconductor layer over the third gate insulating layer; and

a first capacitor comprising;

a first electrode formed a same layer as the first gate electrode; and

a second electrode,

a second capacitor comprising;

the second electrode; and

a third electrode,

wherein the insulating layer is between the second semiconductor layer and the third gate electrode,

wherein the second semiconductor layer comprises an oxide semiconductor,

wherein the third gate electrode is over and in contact with the second gate insulating layer,

wherein the third electrode is electrically connected to the second gate electrode, and

wherein the second gate electrode is electrically connected to one of a source and a drain of the second transistor.

15. The semiconductor device according to claim 14, wherein the first transistor is formed using a silicon substrate.

16. The semiconductor device according to claim 14, wherein the insulating layer has a leveled upper surface.

17. The semiconductor device according to claim 14, wherein a top surface of the second gate electrode is not covered by the insulating layer.

18. The semiconductor device according to claim 14, wherein the circuit is a memory element.

19. The semiconductor device according to claim 14, wherein the third gate electrode is formed from a same layer as the second gate electrode.