Silicon carbide semiconductor device

• US 10,424,642 B2
• Filed: 09/08/2016
• Issued: 09/24/2019
• Est. Priority Date: 09/09/2015
• Status: Active Grant

• Current Assignee: Sumitomo Electric Industries Limited (Sumitomo Corporation)
• Original Assignee: Sumitomo Electric Industries Limited (Sumitomo Corporation)
• Inventors: Shiomi, Hiromu, Kitai, Hidenori, Fukuda, Kenji, Tamaso, Hideto
• Primary Examiner(s): Rodela, Eduardo A
• Application Number:
  US15/755,828
• Publication Number:
  US 20180331209A1
• Time in Patent Office: 1,111 Days
• CPC Class Codes: H01L 21/0465 using masks
• CPC Class Codes: H01L 21/049 Conductor-insulator-semiconductor electrodes, e.g. MIS contacts
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66325 controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
• CPC Class Codes: H01L 29/66333 Vertical insulated gate bipolar transistors
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7393 Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7396 with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7802 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7823 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

The current diffusion layer is interposed between the divided portions of the first base region. The second base region is provided adjacent to both sides of the trench current diffusion layer. The body region is provided on the trench current diffusion layer and the second base region. The source region is provided on the body region. The trench is provided to extend from a surface of the source region to the trench current diffusion layer through the source region and the body region. The trench has a bottom surface that is separated from and overlaps with the center portion of the first base region in a perpendicular direction. A width of the center portion in a horizontal direction is larger than a width of the bottom surface of the trench.

Claims

1. A silicon carbide semiconductor device comprising:

a substrate having a first conductivity type and composed of silicon carbide;

a drift layer provided on the substrate, the drift layer having the first conductivity type, the drift layer being composed of silicon carbide;

a first base region provided on the drift layer, the first base region being divided into a center portion and side portions adjacent to both sides of the center portion, the first base region having a second conductivity type, the first base region being composed of silicon carbide;

a current diffusion layer interposed between the divided portions of the first base region;

a trench current diffusion layer provided on the first base region and the current diffusion layer, the trench current diffusion layer having the first conductivity type, the trench current diffusion layer being composed of silicon carbide,

a second base region provided adjacent to both sides of the trench current diffusion layer, the second base region having the second conductivity type, the second base region being composed of silicon carbide;

a body region provided on the trench current diffusion layer and the second base region, the body region having the second conductivity type, the body region being composed of silicon carbide;

a source region provided on the body region, the source region having the first conductivity type, the source region being composed of silicon carbide;

a contact region having the second conductivity type, the contact region being composed of silicon carbide;

a trench provided to extend from a surface of the source region to the trench current diffusion layer through the source region and the body region;

a gate insulating oxide film provided to cover an inner wall surface of the trench and a portion of the source region;

a gate electrode provided in the trench;

a source electrode that covers a portion of the source region and the contact region, the source electrode being electrically connected to the body region; and

a drain electrode provided on a backside surface of the substrate,

the trench having a bottom surface that is separated from and overlaps with the center portion of the first base region in a perpendicular direction, a width of the center portion in a horizontal direction being larger than a width of the bottom surface of the trench.

2. The silicon carbide semiconductor device according to claim 1, wherein the bottom surface of the trench is separated from the center portion by equal to or more than 0.05 μ

m and equal to or less than 0.5 μ

m in the perpendicular direction.

3. The silicon carbide semiconductor device according to claim 2, wherein the width of the center portion in the horizontal direction is larger than the width of the bottom surface of the trench by equal to or more than 0.1 μ

m and equal to less than 0.5 μ

m.

4. The silicon carbide semiconductor device according to claim 3, wherein an impurity concentration of the current diffusion layer is equal to or more than 1.0×

10¹⁶ cm<sup>−

3</sup> and equal to or less than 4.0×

10¹⁷ cm<sup>−

3</sup>, a width of the current diffusion layer in the horizontal direction between the center portion and each of the side portions of the first base region is equal to or more than 0.7 μ

m and equal to or less than 1.5 μ

m.

5. The silicon carbide semiconductor device according to claim 4, wherein

a thickness of the body region in the perpendicular direction is equal to or more than 0.5 μ

m and equal to or less than 1.5 μ

m, and an impurity concentration of the body region is equal to or more than 1.0×

10¹⁶ cm<sup>−

3</sup> and equal to or less than 3.0×

10¹⁷ cm<sup>−

3</sup>,

a thickness of the source region in the perpendicular direction is equal to or more than 0.1 μ

m and equal to or less than 0.4 μ

m, and an impurity concentration of the source region is equal to or more than 2.0×

10¹⁸ cm<sup>−

3</sup> and equal to or less than 1.0×

10²⁰ cm<sup>−

3</sup>, and

a thickness of the trench current diffusion layer in the perpendicular direction is equal to or more than 0.3 μ

m and equal to or less than 1.0 μ

m, and an impurity concentration of the trench current diffusion layer is equal to or more than 5.0×

10¹⁶ cm<sup>−

3</sup> and equal to or less than 1.0×

10¹⁷ cm<sup>−

3</sup>.

6. The silicon carbide semiconductor device according to claim 4, wherein

a first separation distance between the center portion of the first base region and each of the side portions of the first base region in the horizontal direction is larger than a second separation distance between the center portion of the first base region and an end portion of the second base region in the horizontal direction, and

a difference between the first separation distance and the second separation distance is equal to or more than 0.2 μ

m and is equal to or less than a thickness of the first base region and equal to or less than 0.6 μ

m.

7. The silicon carbide semiconductor device according to claim 6, wherein

the center portion of the first base region is connected to each of the side portions of the first base region by first base region connection portions, and

the first base region connection portions are cyclically provided in a long side direction of the first base region.

8. The silicon carbide semiconductor device according to claim 7, wherein an interval between two adjacent first base region connection portions of the first base region connection portions in the long side direction is equal to or more than 10 μ

m and equal to or less than 200 μ

m.