Power device with high aspect ratio trench contacts and submicron pitches between trenches
First Claim
1. A semiconductor power device disposed in a semiconductor substrate including an active cell area and a termination area wherein the semiconductor power device further comprising:
- a plurality of gate trenches formed at a top portion of the semiconductor substrate in the active cell area wherein each of the gate trenches is partially filled with a conductive gate material with a top portion of the gate trenches covered by a high density plasma (HDP) insulation layer wherein the HDP insulation layer vertically sticks out above the gate trenches;
spacers attached to a top portion of the HDP insulation layer above the gate trenches and exposing a top surface of mesa areas of the semiconductor substrate between the gate trenches; and
each of the mesa areas between the gate trenches having a deep contact trench vertically aligned with the spacers and extending vertically below a top surface of the conductive gate material partially filling the gate trenches wherein the deep contact trenches are filled with a source/body contact material and the gate trenches laterally extends to the termination area constituting a gate pickup trench filled with the conductive gate material therein covered by the HDP layer and a borophosphosilicate (BPSG) insulation layer with a gate contact trench opened through the HDP insulation layer and the BPSG insulation layer to contact a gate metal layer above the BPSG insulation layer.
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Abstract
This invention discloses a semiconductor power device disposed in a semiconductor substrate including an active cell areas and a termination area. The semiconductor power device further comprises a plurality of gate trenches formed at a top portion of the semiconductor substrate in the active cell area wherein each of the gate trenches is partially filled with a conductive gate material with a top portion of the trenches filled by a high density plasma (HDP) insulation layer. The semiconductor power device further comprises mesa areas of the semiconductor substrate disposed between the gate trenches wherein the mesa areas are recessed and having a top mesa surface disposed vertically below a top surface of the HDP insulation layer wherein the HDP insulation layer covering over the conductive gate material constituting a stick-out boundary-defining layer surrounding the recessed mesa areas in the active cell areas between the gate trenches.
7 Citations
13 Claims
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1. A semiconductor power device disposed in a semiconductor substrate including an active cell area and a termination area wherein the semiconductor power device further comprising:
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a plurality of gate trenches formed at a top portion of the semiconductor substrate in the active cell area wherein each of the gate trenches is partially filled with a conductive gate material with a top portion of the gate trenches covered by a high density plasma (HDP) insulation layer wherein the HDP insulation layer vertically sticks out above the gate trenches; spacers attached to a top portion of the HDP insulation layer above the gate trenches and exposing a top surface of mesa areas of the semiconductor substrate between the gate trenches; and each of the mesa areas between the gate trenches having a deep contact trench vertically aligned with the spacers and extending vertically below a top surface of the conductive gate material partially filling the gate trenches wherein the deep contact trenches are filled with a source/body contact material and the gate trenches laterally extends to the termination area constituting a gate pickup trench filled with the conductive gate material therein covered by the HDP layer and a borophosphosilicate (BPSG) insulation layer with a gate contact trench opened through the HDP insulation layer and the BPSG insulation layer to contact a gate metal layer above the BPSG insulation layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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Specification