Super long channel device within VFET architecture

• US 10,424,663 B2
• Filed: 11/15/2017
• Issued: 09/24/2019
• Est. Priority Date: 05/23/2017
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bergendahl, Marc A., Cheng, Kangguo, Karve, Gauri, Lie, Fee Li, Miller, Eric R., Sporre, John R., Teehan, Sean
• Primary Examiner(s): Fan, Bo
• Application Number:
  US15/813,523
• Publication Number:
  US 20180342615A1
• Time in Patent Office: 678 Days
• Field of Search: 438212, 438283, 438583
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/4958 with a multiple layer structure
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors

Abstract

Embodiments are directed to methods and resulting structures for a vertical field effect transistor (VFET) having a super long channel. A pair of semiconductor fins is formed on a substrate. A semiconductor pillar is formed between the semiconductor fins on the substrate. A region that extends under all of the semiconductor fins and under part of the semiconductor pillar is doped. A conductive gate is formed over a channel region of the semiconductor fins and the semiconductor pillar. A surface of the semiconductor pillar serves as an extended channel region when the gate is active.

Claims

1. A method for forming a semiconductor device, the method comprising:

forming a pair of semiconductor fins on a substrate;

forming a semiconductor pillar between the semiconductor fins on the substrate;

forming a bottom doped region that extends under all of the semiconductor fins and under part of the semiconductor pillar;

recessing the semiconductor pillar below a surface of the semiconductor fins; and

forming a conductive gate over a channel region of the semiconductor fins and the semiconductor pillar.

2. The method of claim 1 further comprising doping the semiconductor pillar.

3. The method of claim 1 further comprising forming a thick oxide layer between the conductive gate and the semiconductor fins and the semiconductor pillar.

4. The method of claim 1 further comprising forming a bottom spacer between the conductive gate and the bottom doped region.

5. The method of claim 1 further comprising forming a top spacer on the conductive gate.

6. The method of claim 1 further comprising forming top doped regions on exposed surfaces of the semiconductor fins.

7. The method of claim 6 further comprising forming a conductive contact on the top doped regions.

8. The method of claim 7 further comprising forming a gate contact on the conductive gate and over the semiconductor pillar.

9. The method of claim 1, wherein a thickness of the semiconductor pillar is larger than a thickness of the semiconductor fins.