Operational amplifier with constant transconductance bias circuit and method using the same

• US 10,425,043 B1
• Filed: 05/03/2018
• Issued: 09/24/2019
• Est. Priority Date: 05/03/2018
• Status: Active Grant

• Current Assignee: Novatek Microelectronics Corporation (Novatek Microelectronics Corp Limited)
• Original Assignee: Novatek Microelectronics Corporation (Novatek Microelectronics Corp Limited)
• Inventors: Cheng, Jhih-Siou, Liang, Keko-Chun
• Primary Examiner(s): Nguyen, Patricia T
• Application Number:
  US15/970,872
• Time in Patent Office: 509 Days
• CPC Class Codes: H03F 1/301 in MOSFET amplifiers H03F1/303, H03F1/305, H03F1/308 take precedence
• CPC Class Codes: H03F 2200/18 the bias of the gate of a FET being controlled by a control signal
• CPC Class Codes: H03F 2203/45112 the biasing of the differential amplifier being controlled from the input or the output signal
• CPC Class Codes: H03F 2203/45244 the differential amplifier contains one or more explicit bias circuits, e.g. to bias the tail current sources, to bias the load transistors
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45269 Complementary non-cross coupled types
• CPC Class Codes: H03F 3/45632 in differential amplifiers with FET transistors as the active amplifying circuit H03F3/4578 takes precedence

Abstract

An operational amplifier with a constant transconductance bias circuit and a method thereof are introduced. The operational amplifier includes a differential difference amplifier and the constant transconductance bias circuit. The differential difference amplifier has at least one first differential transistor pair and at least one second differential transistor pair. The constant transconductance bias circuit is electrically connected to the differential difference amplifier, and configured to output a first bias voltage to bias the at least one first differential transistor pair and output a second bias voltage to bias the at least one second differential transistor pair. The first bias voltage and the second bias voltage are configured to maintain constant transconductance of the differential difference amplifier.

Claims

1. An operational amplifier, comprising:

a differential difference amplifier, having at least one first differential transistor pair and at least one second differential transistor pair; and

a constant transconductance bias circuit, electrically connected to the differential difference amplifier, outputting a first bias voltage to bias the at least one first differential transistor pair and outputting a second bias voltage to bias the at least one second differential transistor pair,

wherein the first bias voltage and the second bias voltage are configured to maintain constant Gm of the differential difference amplifier,

wherein the differential difference amplifier comprises;

at least one first bias transistor, coupled to the at least one first differential transistor pair, wherein a control terminal of the at least one first bias transistor receives the first bias voltage to bias the at least one first differential transistor pair; and

at least one second bias transistor, coupled to the at least one second differential transistor pair, wherein a control terminal of the at least one second bias transistor receives the second bias voltage to bias the at least one second differential transistor pair.

2. The operation amplifier of claim 1, the at least one first differential transistor pair has a first conductivity type, the at least one second differential transistor pair has a second conductivity type, and the first conductivity type is different from the second conductivity type.

3. The operational amplifier of claim 1, wherein the differential difference amplifier further comprises:

at least one input terminal, each of the at least one input terminal is coupled to a transistor of the at least one first differential transistor pair and a transistor of the at least one second differential transistor pair,

an output terminal, coupled to the other transistor of the at least one first differential transistor pair and the other transistor of the at least one second differential transistor pair.

4. The operational amplifier of claim 3, wherein

the at least one input terminal of the differential difference amplifier is configured to receive at least one input signal, and

the output terminal of the differential difference amplifier is configured to output an interpolation signal of at least one input signal.

5. The operation amplifier of claim 4, wherein

the at least one input signal comprises a plurality of predetermined input voltage signals, and

the at least one input terminal comprises a first terminal, a second terminal, a third terminal and a fourth terminal, wherein at least two of the first terminal, second terminal and the third terminal receive the same input voltage signal among the predetermined input voltage signal.

6. The operational amplifier of claim 3, wherein

the interpolation signal is obtained according to Gm values of the at least one first differential transistor pair, Gm values of the at least one second differential transistor pair, and the at least one input signal.

7. The operational amplifier of claim 1, wherein the constant Gm bias circuit comprises:

a first constant Gm bias circuit, generating the first bias voltage to bias the at least one first differential transistor pair; and

a second constant Gm bias circuit, generating the second bias voltage to bias the at least one second differential transistor pair.

8. The operational amplifier of claim 7, wherein each of the first constant Gm bias circuit and the second constant transconductance bias circuit comprises:

a first transistor pair;

a second transistor pair, coupled to the first transistor pair through a first node and a second node; and

a transconductance setting transistor, coupled to the first transistor pair,

wherein transconductance values of the at least one first differential transistor pair are inversely proportional to a resistance value of the transconductance setting transistor, and

transconductance values of the at least one second differential transistor pair are inversely proportional to a resistance value of the Gm setting transistor.

9. The operational amplifier of claim 8, wherein the first transistor pair has a first conductivity type, the second transistor pair has a second conductivity type.

10. The operational amplifier of claim 8, wherein

the first node is coupled to control terminals of the second transistor pair,

the second node is coupled to control terminals of the first transistor pair, and

the first node provides the first bias voltage or the second bias voltage to the differential difference amplifier.

11. The operational amplifier of claim 7, wherein

the at least one first differential transistor pair comprises a first transistor pair group and a second transistor pair group,

the at least one second differential transistor pair comprises a third transistor pair group and a fourth transistor pair group,

the first transistor pair is biased by the first bias voltage,

the second transistor pair is biased by a third bias voltage,

the third transistor pair is biased by the second bias voltage, and

the fourth transistor pair is biased by a fourth bias voltage.

12. The operational amplifier of claim 11, wherein the constant Gm bias circuit further comprises:

a third constant Gm bias circuit, generating the third bias voltage; and

a fourth constant Gm bias circuit, generating the fourth bias voltage.

13. A method for biasing a differential difference amplifier having at least one first differential transistor pair, at least one second differential transistor pair, at least one first bias transistor and at least one second bias transistor, the method comprising:

generating a first bias voltage and a second bias voltage; and

outputting the first bias voltage to bias the at least one first differential transistor pair and the second bias voltage to bias the at least one second differential transistor pair;

wherein the first bias voltage and the second bias voltage are configured to maintain constant transconductance of the differential difference amplifier,

wherein the at least one first bias transistor is coupled to the at least one first differential transistor pair, a control terminal of the at least one first bias transistor receives the first bias voltage to bias the at least one first differential transistor pair, the at least one second bias transistor is coupled to the at least one second differential transistor pair, and a control terminal of the at least one second bias transistor receives the second bias voltage to bias the at least one second differential transistor pair.

14. The method of claim 13, further comprising:

providing at least one input signal to at least one input terminal of the differential difference amplifier;

performing an interpolation operation on the at least one input signal to output an interpolation signal.

15. The method of claim 14, wherein the interpolation signal is obtained according to transconductance values of the at least one first differential transistor pair, transconductance values of the at least one second differential transistor pair, and the at least one input signal.

16. The method of claim 15, wherein the at least one input signal comprises a plurality of predetermined input voltage signals.

17. The method of claim 13, wherein

the at least one first differential transistor pair comprises a first transistor pair group and a second transistor pair group,

the at least one second differential transistor pair comprises a third transistor pair group and a fourth transistor pair group,

wherein the first transistor pair group is biased by the first bias voltage, the second transistor pair group is biased by a third bias voltage, the third transistor pair group is biased by the second bias voltage, and the fourth transistor pair group is biased by a fourth bias voltage.

18. The method of claim 13, wherein the at least one first differential transistor pair has a first conductivity type, the at least one second differential transistor pair has a second conductivity type, and the first conductivity type is different from the second conductivity type.