Field programmable logic array

• US 10,425,081 B2
• Filed: 01/28/2015
• Issued: 09/24/2019
• Est. Priority Date: 01/28/2015
• Status: Active Grant

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Sakata, Teruaki, Yamada, Tsutomu, Hirotsu, Teppei
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): Alshack, Osman M
• Application Number:
  US15/546,694
• Publication Number:
  US 20180278254A1
• Time in Patent Office: 1,700 Days
• Field of Search: 714718, 714746, 714758, 714759, 714763, 714764
• CPC Class Codes: G01R 31/31703 Comparison aspects, e.g. signature analysis, comparators concerning scan tests G01R31/318566; concerning testers G01R31/3193
• CPC Class Codes: G01R 31/318519 Test of field programmable gate arrays [FPGA]
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 29/12 Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: H03K 19/17732 Macroblocks
• CPC Class Codes: H03K 19/17764 for reliability

Abstract

To realize control of a system for which a high level of safety is demanded by one SRAM-type FPGA, it is to eliminate a possibility that an undesirable control signal is output to the outside of the FPGA because of influence of failure by a soft error and the like and a problem. To solve this problem, there is provided a hard macro having fixed circuitry structure, programmable logic arranged via an interval close to the hard macro and having a changeable circuitry structure, and an I/F circuit which is provided inside the programmable logic and outputs a processing result in the programmable logic to the hard macro. It is a characteristic that the I/F circuit monitors soundness of the programmable logic and stops output of the processing result to be transmitted to the hard macro on the basis of a monitoring result.

Claims

1. A field programmable logic array, comprising:

a hard macro having a fixed circuitry structure;

programmable logic arranged via an interval close to the hard macro and having a programmable circuitry structure; and

an I/F circuit which is provided in the programmable logic and outputs a processing result in the programmable logic to the hard macro,

wherein the I/F circuit monitors soundness of the programmable logic and stops output of the processing result to be transmitted to the hard macro on the basis of a result of the monitoring;

wherein the programmable logic;

disconnects connection to the hard macro and executes arithmetic processing of a signal to be output to the hard macro;

is connected to the hard macro after the arithmetic processing is finished and transmits a processing result to the hard macro;

disconnects the connection to the hard macro after the processing result is transmitted to the hard macro; and

the hard macro outputs the processing result to the outside of the field programmable logic array while the connection to the programmable logic is disconnected.

2. The field programmable logic array according to claim 1,

wherein the I/F circuit monitors the soundness of the programmable logic according to a control signal from the hard macro.

3. The field programmable logic array according to claim 2,

wherein the I/F circuit monitors using a diagnostic result of the programmable logic by using a cyclic redundancy check of a configuration random access memory.

4. The field programmable logic array according to claim 2,

wherein the I/F circuit monitors using a diagnostic result of the programmable logic by using an error-correcting code of a configuration random access memory.

5. The field programmable logic array according to claim 1,

wherein a higher level of safety is demanded for an application executed in the hard macro than an application executed in the programmable logic.

6. The field programmable logic array according to claim 1,

wherein a signal output from the programmable logic to the hard macro is multiplexed, and

the hard macro is provided with comparator circuits that compare the multiplexed signals and when the multiplexed signals discord as a result of the comparison, stops output of the signal to the outside of the field programmable logic array.

7. The field programmable logic array according to claim 1,

wherein the hard macro is provided with communication ports which are connected to the I/F circuit and are disconnectable from the I/F circuit.

8. The field programmable logic array according to claim 1,

wherein external terminals of the field programmable logic array are divided into:

external terminals connected only to the hard macro; and

the external terminals connected only to the programmable logic.

9. The field programmable logic array according to claim 8,

wherein the external terminals are installed on four sides of a package, and

the hard macro is provided next to any side of the package.

10. The field programmable logic array according to claim 8,

wherein external terminals are installed at the bottom of a package.

11. The field programmable logic array according to claim 1,

wherein the hard macro is arranged over external pins of the field programmable logic array, and

the programmable logic is arranged further on the hard macro.