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Field programmable logic array

  • US 10,425,081 B2
  • Filed: 01/28/2015
  • Issued: 09/24/2019
  • Est. Priority Date: 01/28/2015
  • Status: Active Grant
First Claim
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1. A field programmable logic array, comprising:

  • a hard macro having a fixed circuitry structure;

    programmable logic arranged via an interval close to the hard macro and having a programmable circuitry structure; and

    an I/F circuit which is provided in the programmable logic and outputs a processing result in the programmable logic to the hard macro,wherein the I/F circuit monitors soundness of the programmable logic and stops output of the processing result to be transmitted to the hard macro on the basis of a result of the monitoring;

    wherein the programmable logic;

    disconnects connection to the hard macro and executes arithmetic processing of a signal to be output to the hard macro;

    is connected to the hard macro after the arithmetic processing is finished and transmits a processing result to the hard macro;

    disconnects the connection to the hard macro after the processing result is transmitted to the hard macro; and

    the hard macro outputs the processing result to the outside of the field programmable logic array while the connection to the programmable logic is disconnected.

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