Divider-less phase locked loop
First Claim
1. A divider-less phase locked loop (PLL), comprising:
- a phase frequency detector (PFD), generating an up signal and a down signal;
a charge pump (CP), electrically connected to the PFD, and generating a voltage control signal according to the up signal and the down signal;
a voltage controlled oscillator (VCO), electronically connected to the CP, and generating an output signal according to the voltage control signal;
a delay unit, receiving a reference signal, and delaying the reference signal to generate a delay signal; and
a clock gating unit, electrically connected to the PFD, the VCO, and the delay unit;
wherein the clock gating unit samples the output signal according to the delay signal to generate a feedback signal;
wherein the PFD receives the reference signal and the feedback signal, and generates the up signal and the down signal according to the reference signal and the feedback signal.
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Accused Products
Abstract
A divider-less phase locked loop (PLL) includes a phase frequency detector (PFD), a charge pump (CP), a voltage controlled oscillator (VCO), a delay unit, and a clock gating unit. The PFD is electrically connected to the VCO through the CP, and the CP outputs a voltage control signal to the VCO. The VCO generates an output signal. The delay unit receives and delays a reference signal to generate a delay signal. The clock gating unit samples the output signal according to the delay signal. Since the clock gating unit samples the output signal according to the delay signal, the divider-less PLL does not need to include a divider to divide a frequency of the output signal. Therefore, power consumption of the divider-less PLL can be reduced.
51 Citations
10 Claims
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1. A divider-less phase locked loop (PLL), comprising:
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a phase frequency detector (PFD), generating an up signal and a down signal; a charge pump (CP), electrically connected to the PFD, and generating a voltage control signal according to the up signal and the down signal; a voltage controlled oscillator (VCO), electronically connected to the CP, and generating an output signal according to the voltage control signal; a delay unit, receiving a reference signal, and delaying the reference signal to generate a delay signal; and a clock gating unit, electrically connected to the PFD, the VCO, and the delay unit;
wherein the clock gating unit samples the output signal according to the delay signal to generate a feedback signal;wherein the PFD receives the reference signal and the feedback signal, and generates the up signal and the down signal according to the reference signal and the feedback signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification