Extremely-fine resolution sub-ranging current mode Digital-Analog-Converter using Sigma-Delta modulators

• US 10,425,099 B1
• Filed: 11/29/2018
• Issued: 09/24/2019
• Est. Priority Date: 11/29/2018
• Status: Active Grant

• Current Assignee: Ciena Corporation
• Original Assignee: Ciena Corporation
• Inventors: Aouini, Sadok, Emara, Ahmed, Roberts, Gordon, Parvizi, Mahdi, Ben-Hamida, Naim
• Primary Examiner(s): Nguyen, Khai M
• Application Number:
  US16/203,738
• Time in Patent Office: 299 Days
• Field of Search: 341118, 341120, 341143-145
• CPC Class Codes: H03M 1/1009 Calibration
• CPC Class Codes: H03M 1/742 using current sources as quantisation value generators
• CPC Class Codes: H03M 3/358 of non-linear distortion, e.g. instability avoiding instability by structural design H03M3/44
• CPC Class Codes: H03M 3/38 Calibration
• CPC Class Codes: H03M 3/392 Arrangements for selecting among plural operation modes, e.g. for multi-standard operation
• CPC Class Codes: H03M 3/50 Digital/analogue converters using delta-sigma modulation as an intermediate step digital delta-sigma modulators per se H03M7/3004
• CPC Class Codes: H03M 3/51 Automatic control for modifying converter range

Abstract

A X-bit Digital-to-Analog Converter (DAC) circuit includes an effective X/2-bit coarse DAC configured to produce a coarse bitstream (CBS) from a digital input DC₁ using an n^th order Sigma-Delta (ΣΔ) modulator, and to provide a coarse current source based on the CBS, wherein X is an even integer and n is an integer; an effective X/2-bit fine DAC configured to produce a fine bitstream (FBS) from a digital input DC₂ using a 1^st order ΣΔ modulator, and to provide a fine current source based on the FBS; and an output configured to form a voltage from the combination of the coarse current source and the fine current source.

Claims

1. A X-bit Digital-to-Analog Converter (DAC) circuit comprising:

an effective X/2-bit coarse DAC configured to produce a coarse bitstream (CBS) from a digital input DC₁ using an n^th order Sigma-Delta (Σ

Δ

) modulator, and to provide a coarse current source based on the CBS, wherein X is an even integer and n is an integer;

an effective X/2-bit fine DAC configured to produce a fine bitstream (FBS) from a digital input DC₂ using a 1^st order Σ

Δ

modulator, and to provide a fine current source based on the FBS; and

an output configured to form a voltage from the combination of the coarse current source and the fine current source.

2. The DAC circuit of claim 1, wherein

a first 1-bit DAC is configured to provide the coarse current source based on the CBS, and

a second 1-bit DAC is configured to provide the fine current source based on the FBS.

3. The DAC circuit of claim 2, wherein a combination of the Σ

Δ

modulators and each of the first 1-bit DAC and the second 1-bit DAC provides the X-bit resolution.

4. The DAC circuit of claim 2, wherein each of the 1-bit DACs are configured to provide a current value if the respective CBS and FBS are logically high and no current if the respective CBS and FBS are logically low.

5. The DAC circuit of claim 1, wherein the value of n represents the Σ

Δ

modulator order to be used for the coarse DAC and is selected based on the desired linear range of operation.

6. The DAC circuit of claim 1, further comprising

a Low Pass Filter (LPF) configured to receive the combination of the coarse current source and the fine current source and to provide the output.

7. The DAC circuit of claim 6, wherein an order of the LPF matches an order of the n^th order Σ

Δ

modulation.

8. The DAC circuit of claim 1, wherein the DAC circuit is calibrated by matching the coarse current source and the fine current source.

9. An integrated circuit comprising:

a coarse Digital-to-Analog Converter (DAC) including

an n^th order Sigma-Delta (Σ

Δ

) modulator that receives a digital input DC₁ and outputs a coarse bitstream (CBS), and

a coarse 1-bit DAC that operates on the CBS to provide a coarse current source;

a fine DAC including

an 1^st order Σ

Δ

modulator that receives a digital input DC₂ and outputs a fine bitstream (FBS), and

a fine 1-bit DAC that operates on the FBS to provide a fine current source;

a summing element connected to the coarse current source and the fine current source; and

a Low Pass Filter (LPF) connected to the summing element and configured to provide a voltage at an output, the voltage formed as a combination of the coarse current source and the fine current source.

10. The integrated circuit of claim 9, wherein each of the coarse 1-bit DAC and the fine 1-bit DAC are configured to provide a current value if the respective CBS and FBS are logically high and no current if the respective CBS and FBS are logically low.

11. The integrated circuit of claim 9, wherein a value of n in the n^th order Σ

Δ

modulator is selected based on a linear range of operation.

12. The integrated circuit of claim 9, wherein an order of the LPF matches an order of the n^th order Σ

Δ

modulation.

13. The integrated circuit of claim 9, further comprising

level-shifting circuitry configured to convert the CBS and the FBS from a full swing input waveform to a moderate swing input waveform.

14. The integrated circuit of claim 9, wherein the integrated circuit is calibrated by matching the coarse current source and the fine current source.

15. A method of operating a Digital-to-Analog Converter (DAC) circuit comprising:

at a coarse DAC, receiving a digital input DC₁, applying n^th order Sigma-Delta (Σ

Δ

) modulation on the digital input DC₁ to produce a coarse bitstream (CBS), and providing a coarse current source based on the CBS;

at a fine DAC, receiving a digital input DC₂, applying 1^st order Sigma-Delta (Σ

Δ

) modulation on the digital input DC₂ to produce a fine bitstream (FBS), and providing a fine current source based on the FBS; and

providing a voltage at an output, the voltage formed as a combination of the coarse current source and the fine current source.

16. The method of claim 15, wherein

a first 1-bit DAC is configured to provide the coarse current source based on the CBS;

and

a second 1-bit DAC is configured to provide the fine current source based on the FBS.

17. The method of claim 15, wherein the value of n represents the Σ

Δ

modulator order to be used for the coarse DAC and is selected based on the desired linear range of operation.

18. The method of claim 15, further comprising

utilizing a Low Pass Filter (LPF) to receive the combination of the coarse current source and the fine current source and to provide the output.

19. The method of claim 15, further comprising

utilizing level-shifting circuitry to convert the CBS and the FBS from a full swing input waveform to a moderate swing input waveform.

20. The method of claim 15, further comprising

calibrating digitally by matching the coarse current source and the fine current source.