Test device

• US 10,429,878 B2
• Filed: 01/08/2019
• Issued: 10/01/2019
• Est. Priority Date: 01/10/2018
• Status: Active Grant

• Current Assignee: Ememory Technology Inc.
• Original Assignee: Ememory Technology Inc.
• Inventors: Wu, Yu
• Primary Examiner(s): Nash, Gary A
• Application Number:
  US16/242,010
• Publication Number:
  US 20190212763A1
• Time in Patent Office: 266 Days
• Field of Search: 323312, 323315-317
• CPC Class Codes: G01R 31/2855 Environmental, reliability or burn-in testing
• CPC Class Codes: G01R 31/2879 related to electrical aspects, e.g. to voltage or current supply or stimuli or to electrical loads
• CPC Class Codes: G05F 1/575 characterised by the feedback circuit
• CPC Class Codes: G05F 3/262 using field-effect transistors only
• CPC Class Codes: H03F 1/34 Negative-feedback-circuit arrangements with or without positive feedback H03F1/02 - H03F1/30, H03F1/38 - H03F1/50, H03F3/50 take precedence ; for rejection of common mode signals H03F3/45479
• CPC Class Codes: H03F 1/342 in field-effect transistor amplifiers
• CPC Class Codes: H03F 2200/261 Amplifier which being suitable for instrumentation applications
• CPC Class Codes: H03F 3/3027 using a common source driving stage, i.e. inverting stage
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit

Abstract

A test device is provided. An output terminal of an operational amplifier is coupled to a device under test. A current replication circuit copies a current flowing through a charging circuit and a discharge circuit according to voltages of control terminals of the charging circuit and the discharge circuit in the operational amplifier and outputs a test result signal.

Claims

1. A test device, comprising:

an operational amplifier, wherein an output terminal of the operational amplifier is coupled to a negative input terminal of the operational amplifier to form a negative feedback path, the operational amplifier comprising;

a charging circuit providing at least one charging path from an operating voltage of the operational amplifier to the output terminal of the operational amplifier; and

a discharge circuit coupled to a common junction with the charging circuit and the common junction is coupled to the output terminal of the operational amplifier to provide at least one discharge path from the output terminal of the operational amplifier to a ground voltage, wherein the output terminal of the operational amplifier is coupled to a device under test; and

a current replication circuit coupled to control terminals of the charging circuit and the discharge circuit and copying a current flowing through the at least one charging path and the at least one discharge path according to voltages of the control terminals of the charging circuit and the discharge circuit to output a test result signal.

2. The test device of claim 1, wherein the charging circuit comprises at least one first P-type transistor, the discharge circuit comprises at least one first N-type transistor, the at least one first P-type transistor is coupled between the operating voltage and the output terminal of the operational amplifier to provide a first charging path, and the at least one first N-type transistor is coupled between the output terminal of the operational amplifier and the ground voltage to provide a first discharge path.

3. The test device of claim 2, wherein the current replication circuit comprises at least one second P-type transistor and at least one second N-type transistor, the at least one second P-type transistor is connected in series between the operating voltage and an output terminal of the current replication circuit, the at least one second N-type transistor is connected in series between the output terminal of the current replication circuit and the ground voltage, and gates of the at least one second P-type transistor and the at least one second N-type transistor are respectively coupled to gates of the corresponding at least one first P-type transistor and the corresponding at least one first N-type transistor.

4. The test device of claim 3, wherein the charging circuit further comprises at least one third P-type transistor, the discharge circuit comprises at least one third N-type transistor, the at least one third P-type transistor and the at least one third N-type transistor are connected in series between the operating voltage and the ground voltage, the at least one third P-type transistor provides a second charging path, and the at least one third N-type transistor provides a second discharge path.

5. The test device of claim 4, wherein the current replication circuit further comprises at least one fourth P-type transistor and at least one fourth N-type transistor, the at least one fourth P-type transistor and the at least one fourth N-type transistor are connected in series between the operating voltage and the ground voltage, and gates of the at least one fourth P-type transistor and the at least one fourth N-type transistor are respectively coupled to gates of the corresponding at least one third P-type transistor and the corresponding at least one third N-type transistor.

6. The test device of claim 1, further comprising:

a comparison circuit coupled to the current replication circuit to compare the test result signal with a reference signal to output a comparison signal.

7. The test device of claim 1, wherein the device under test comprises a chip under test.

8. The test device of claim 1, wherein the operational amplifier comprises a single-stage operational amplifier.

9. The test device of claim 8, wherein the charging circuit comprises a first P-type transistor, a source and a drain of the first P-type transistor are respectively coupled to the operating voltage and the device under test, a gate of the first P-type transistor is coupled to the current replication circuit, the discharge circuit comprises a first N-type transistor, a drain of the first N-type transistor is coupled to the drain of the first P-type transistor, and a gate of the first N-type transistor is coupled to the drain of the first N-type transistor and the current replication circuit, the operational amplifier further comprising:

a second P-type transistor, wherein a source and a gate of the second P-type transistor are respectively coupled to the operating voltage and the gate of the first P-type transistor, and the gate and a drain of the second P-type transistor are coupled to each other;

a second N-type transistor, wherein a drain of the second N-type transistor is coupled to the drain of the second P-type transistor, and a gate of the second N-type transistor receives a test voltage; and

a third N-type transistor, wherein a drain of the third N-type transistor is coupled to sources of the first N-type transistor and the second N-type transistor, a source of the third N-type transistor is coupled to the ground voltage, and a gate of the third N-type transistor receives a bias voltage.

10. The test device of claim 1, wherein the operational amplifier comprises a two-stage operational amplifier.

11. The test device of claim 10, wherein the operational amplifier further comprises:

a first P-type transistor, wherein a source of the first P-type transistor is coupled to the operating voltage;

a first N-type transistor, wherein a drain of the first N-type transistor is coupled to a drain of the first P-type transistor, and a gate of the first N-type transistor receives a test voltage;

a second P-type transistor, wherein a source and a gate of the second P-type transistor are respectively coupled to the operating voltage and a gate of the first P-type transistor, and the gate and a drain of the second P-type transistor are coupled to each other;

a second N-type transistor, wherein a drain of the second N-type transistor is coupled to the drain of the second P-type transistor; and

a third N-type transistor, wherein a drain of the third N-type transistor is coupled to sources of the first N-type transistor and the second N-type transistor, a source of the third N-type transistor is coupled to the ground voltage, a gate of the third N-type transistor receives a bias voltage, the charging circuit comprises a fourth P-type transistor, a source and a drain of the fourth P-type transistor are respectively coupled to the operating voltage and the device under test, a gate of the fourth P-type transistor is coupled to the drain of the first P-type transistor and the current replication circuit, the discharge circuit comprises a fourth N-type transistor, a drain of the fourth N-type transistor is coupled to the drain of the fourth P-type transistor and a gate of the second N-type transistor, a gate of the fourth N-type transistor is coupled to the gate of the third N-type transistor, and a source of the fourth N-type transistor is coupled to the ground voltage.

12. The test device of claim 1, wherein the operational amplifier comprises a telescopic operational amplifier.

13. The test device of claim 12, wherein the charging circuit comprises a first P-type transistor and a fourth P-type transistor, and the discharge circuit comprises a second N-type transistor and a fourth N-type transistor, the operational amplifier further comprising:

a second P-type transistor, wherein a gate of the second P-type transistor is coupled to a gate of the first P-type transistor and receives a first bias voltage;

a third P-type transistor, wherein a gate of the third P-type transistor is coupled to a gate of the fourth P-type transistor and a drain of the second P-type transistor, the first P-type transistor and the fourth P-type transistor are connected in series between the operating voltage and the device under test, and the gates of the first P-type transistor and the fourth P-type transistor are coupled to the current replication circuit;

a first N-type transistor, wherein a gate of the first N-type transistor receives a test voltage;

a third N-type transistor coupled between the second P-type transistor and the first N-type transistor, and a gate of the third N-type transistor receives a second bias voltage; and

a fifth N-type transistor, wherein a drain of the fifth N-type transistor is coupled to sources of the first N-type transistor and the second N-type transistor, a source of the fifth N-type transistor is coupled to the ground voltage, a gate of the fifth N-type transistor receives a third bias voltage, the second N-type transistor and the fourth N-type transistor are coupled between a drain of the first P-type transistor and the fifth N-type transistor, a gate of the second N-type transistor is coupled to a drain of the fourth N-type transistor and the current replication circuit, and a gate of the fourth N-type transistor is coupled to the gate of the third N-type transistor and the current replication circuit.

14. The test device of claim 1, wherein the operational amplifier comprises a folded cascode operational amplifier.

15. The test device of claim 14, wherein the charging circuit comprises a fifth P-type transistor and a seventh P-type transistor, and the discharge circuit comprises a first N-type transistor and a third N-type transistor, the operational amplifier further comprising:

a first P-type transistor, wherein a gate of the first P-type transistor receives a first bias voltage, and a source of the first P-type transistor is coupled to the operating voltage;

a second P-type transistor, wherein a source of the second P-type transistor is coupled to a drain of the first P-type transistor, and a gate of the second P-type transistor receives a test voltage;

a third P-type transistor, wherein a source of the third P-type transistor is coupled to the drain of the first P-type transistor, and a gate of the third P-type transistor is coupled to a drain of the seventh P-type transistor;

a fourth P-type transistor, wherein a gate of the fourth P-type transistor is coupled to a gate of the fifth P-type transistor, and a source of the fourth P-type transistor is coupled to the operating voltage;

a sixth P-type transistor, wherein a gate of the sixth P-type transistor is coupled to a gate of the seventh P-type transistor and receives a second bias voltage, a drain of the sixth P-type transistor is coupled to the gate of the fourth P-type transistor, the fifth P-type transistor and the seventh P-type transistor are connected in series between the operating voltage and the device under test, and the gates of the fifth P-type transistor and the seventh P-type transistor are coupled to the current replication circuit;

a second N-type transistor; and

a fourth N-type transistor and the second N-type transistor are coupled between the sixth P-type transistor and the ground voltage, wherein a gate of the second N-type transistor receives a third bias voltage, a gate of the fourth N-type transistor receives a fourth bias voltage, a drain of the fourth N-type transistor is coupled to the drain of the second P-type transistor, the first N-type transistor and third N-type transistor are coupled between the drain of the seventh P-type transistor and the ground voltage, a gate of the first N-type transistor is coupled to the gate of the second N-type transistor and the current replication circuit, a gate of the third N-type transistor is coupled to the gate of the fourth N-type transistor and the current replication circuit, and a drain of the third N-type transistor is coupled to a drain of the third P-type transistor.