Systems and methods for selectively controlling multithreaded execution of executable code segments

• US 10,430,190 B2
• Filed: 03/15/2013
• Issued: 10/01/2019
• Est. Priority Date: 06/07/2012
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Leidel, John D., Wadleigh, Kevin R., Bolding, Joe, Brewer, Tony, Walker, Dean E.
• Primary Examiner(s): Li, Aimee
• Assistant Examiner(s): Carmichael-Moody, Courtney P
• Application Number:
  US13/834,362
• Publication Number:
  US 20130332711A1
• Time in Patent Office: 2,391 Days
• Field of Search: 712200
• CPC Class Codes: G06F 8/45 Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions
• CPC Class Codes: G06F 9/3009 Thread control instructions
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/30185 according to one or more bits in the instruction, e.g. prefix, sub-opcode
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming

Abstract

Systems and methods which provide a modular processor framework and instruction set architecture designed to efficiently execute applications whose memory access patterns are irregular or non-unit stride are disclosed. A hybrid multithreading framework (HMTF) of embodiments provides a framework for constructing tightly coupled, chip-multithreading (CMT) processors that contain specific features well-suited to hiding latency to main memory and executing highly concurrent applications. The HMTF of embodiments includes an instruction set designed specifically to exploit the high degree of parallelism and concurrency control mechanisms present in the HMTF hardware modules. The instruction format implemented by a HMTF of embodiments is designed to give the architecture, the runtime libraries, and/or the application ultimate control over how and when concurrency between thread cache units is initiated. For example, one or more bit of the instruction payload may be designated as a context switch bit (CTX) for expressly controlling context switching.

Claims

1. A method comprising:

determining, on an instruction-by-instruction basis, instruction control information for selectively controlling multithreaded execution of executable code segments of instructions executable upon one or more processing units of a multicore processor-based system, wherein the instruction control information includes context switching control information configured to inform a processing unit of the one or more processing units of the multicore processor-based system whether to initiate a thread switch from a thread in which an executable code segment of an instruction corresponding to the context switching control information is executed by the processing unit to another thread executed by the processing unit and thread control information configured to designate to the processing unit of the multicore processor-based system between an operand field of an executable code segment of the instruction corresponding to the thread control information (i) indexing to a user data register block of the multicore processor-based system and (ii) indexing to a control register block of the multicore processor-based system, wherein the thread control information comprises information for a plurality of operands of the executable code segment of the instruction corresponding to the thread control information, wherein the information of the thread control information includes information corresponding to each operand of the plurality of operands and independently designates to the processing unit that the corresponding operand indexes to one of the user data register block and the control register block; and

including the instruction control information having the context switching control information and the thread control information in an instruction format having one or more instruction control information fields and one or more executable code segment fields, wherein the thread control information is fully contained in an instruction control information field of the one or more instruction control information fields separate from the plurality of operands contained in the one or more executable code segment fields.

2. The method of claim 1, further comprising:

analyzing code, from which the instructions are generated, for instruction scheduling, wherein the determining instruction control information is based at least in part on the analyzing.

3. The method of claim 2, wherein the analyzing comprises:

analyzing the executable code segments to determine when long latency events will occur.

4. The method of claim 2, wherein the analyzing comprises:

analyzing the executable code segments for pragmas inserted into the code for controlling execution of the instructions.

5. The method of claim 1, wherein the instruction format includes the instruction control information field in which the instruction control information having the context switching control information and the thread control information of the instruction corresponding to the thread control information is carried and the one or more executable code segment fields in which the executable code segment of the instruction corresponding to the thread control information is carried, wherein the one or more executable code segment fields includes the operand field.

6. The method of claim 1, wherein a control register of the control register block comprises a user defined register corresponding to the thread control information.

7. The method of claim 1, wherein a control register of the control register block comprises a macro index indicating a specific case of a payload corresponding to the thread control information.

8. The method of claim 1, wherein a control register of the control register block comprises a thread cache control register corresponding to the thread control information.

9. The method of claim 1, wherein a control register of the control register block comprises context switch information corresponding to the thread control information.

10. The method of claim 1, wherein the instruction control information further includes debugging support and control information configured to support debugging capabilities of the processing unit.

11. The method of claim 10, wherein the debugging support and control information comprises a step bit controlling subsequent execution to progress a single instruction at a time.

12. The method of claim 10, wherein the debugging support and control information comprises a break bit signaling a breakpoint to initiate a context save operation of all currently executing thread cache units of the multicore processor-based system prior to execution of the executable code segment of the instruction corresponding to the thread control information.

13. The method of claim 1, wherein the instruction control information further includes immediate bundling control information configured to signal that a latter instruction unit comprises an immediate value to be bundled with the instruction corresponding to the thread control information.

14. A method comprising:

determining instruction control information for selectively controlling multithreaded execution of executable code segments of instructions executable upon one or more processing units of a multicore processor-based system, wherein the instruction control information of a first instruction unit includes (a) context switching control information configured to inform a processing unit of the one or more processing units of the multicore processor-based system whether to initiate a thread switch from a thread in which an executable code segment of the first instruction unit is executed by the processing unit to another thread executed by the processing unit, (b) thread control information configured to designate to the processing unit of the multicore processor-based system between an operand field of the executable code segment of the first instruction unit (i) indexing to a user data register block of the multicore processor-based system and (ii) indexing to a control register block of the multicore processor-based system, and (c) immediate bundling control information configured to signal that a latter instruction unit comprises an immediate value to be bundled with the first instruction unit, wherein the first instruction unit comprises the executable code segment and the latter instruction unit comprises the immediate value used by the executable code segment of the first instruction unit; and

including the instruction control information having the context switching control information, the thread control information, and the immediate bundling control information in an instruction control field of an instruction format that includes the instruction control field and one or more fields in which a corresponding executable code segment is carried, wherein the one or more fields includes the operand field, wherein the thread control information is fully contained in the instruction control field separate from the operand field; and

wherein the thread control information comprises thread control information for a plurality of operands of the executable code segment of the first instruction unit, wherein thread control information corresponding to each operand independently informs the processing unit whether the corresponding operand relates to the user data register block or the control register block.

15. The method of claim 14, wherein a control register of the control register block comprises a user defined register corresponding to the thread control information.

16. The method of claim 14, wherein a control register of the control register block comprises a macro index indicating a specific case of a payload corresponding to the thread control information.

17. The method of claim 14, wherein a control register of the control register block comprises a thread cache control register corresponding to the thread control information.

18. The method of claim 14, wherein a control register of the control register block comprises context switch information corresponding to the thread control information.

19. The method of claim 14, wherein the instruction control information further includes debugging support and control information configured to support debugging capabilities of the processing unit.

20. The method of claim 19, wherein the debugging support and control information comprises a step bit controlling subsequent execution to progress a single instruction at a time.

21. The method of claim 19, wherein the debugging support and control information comprises a break bit signaling a breakpoint to initiate a context save operation of all currently executing thread cache units of the multicore processor-based system prior to execution of the executable code segment of the first instruction unit.