Synchronization logic for memory requests

• US 10,430,252 B2
• Filed: 11/15/2018
• Issued: 10/01/2019
• Est. Priority Date: 06/13/2016
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Sury, Samantika S., Blankenship, Robert G., Steely, Jr., Simon C.
• Primary Examiner(s): Lane, John A
• Application Number:
  US16/192,322
• Publication Number:
  US 20190087240A1
• Time in Patent Office: Days
• Field of Search: None
• CPC Class Codes: G06F 12/0828 with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/502 using adaptive policy
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In an embodiment, a processor includes a plurality of cores and synchronization logic. The synchronization logic includes circuitry to: receive a first memory request and a second memory request; determine whether the second memory request is in contention with the first memory request; and in response to a determination that the second memory request is in contention with the first memory request, process the second memory request using a non-blocking cache coherence protocol. Other embodiments are described and claimed.

Claims

1. A processor comprising:

a plurality of cores; and

circuitry to;

receive a first memory request from a first core and a second memory request from a second core;

determine whether the second memory request is in contention with the first memory request for a first memory address stored in a third core; and

in response to a determination that the second memory request is in contention with the first memory request, send a blocking-protocol invalidation message to the third core.

2. The processor of claim 1, the circuitry to:

send, to the first core, a non-blocking-protocol invalidation message associated with the second request without waiting for a data response from the third core.

3. The processor of claim 2, the circuitry to:

receive, from the third core, a data response associated with the first request; and

in response to a receipt of the data response from the third core, send, to the first core, a non-blocking-protocol acknowledgement message associated with the first request.

4. The processor of claim 3, the circuitry to:

receive, from the first core, a data response associated with the second request; and

in response to a receipt of the data response from the first core, send, to the second core, a non-blocking-protocol acknowledgement message associated with the second request.

5. The processor of claim 4, the first core comprising cache logic to:

receive the non-blocking-protocol invalidation message associated with the second request; and

store the non-blocking-protocol invalidation message associated with the second request in a memory buffer of the cache logic until a receipt of the non-blocking-protocol acknowledgement message associated with the first request.

6. The processor of claim 5, the cache logic of the first core to:

in response to a receipt of the non-blocking-protocol acknowledgement message associated with the first request;

process data included in the received non-blocking-protocol acknowledgement message to generate processed data;

send a data response including the processed data; and

process the stored non-blocking-protocol invalidation message to invalidate a local copy of the processed data.

7. The processor of claim 1, the circuitry to:

in response to a determination that the second memory request is not in contention with the first memory request, process the second memory request using a blocking cache coherence protocol.

8. A method comprising:

receiving, by synchronization logic, a first memory request from a first core of a processor;

receiving, by the synchronization logic, a second memory request from a second core of the processor;

determining, by the synchronization logic, whether the second memory request is in contention with the first memory request for a first memory address stored in a third core; and

in response to a determination that the second memory request is in contention with the first memory request, the synchronization logic sending a blocking-protocol invalidation message to the third core.

9. The method of claim 8, comprising:

sending, to the first core, a non-blocking-protocol invalidation message associated with the second request without waiting for a data response from the third core.

10. The method of claim 9, comprising:

receiving, from the third core, a data response associated with the first request; and

in response to a receipt of the data response from the third core, sending, to the first core, a non-blocking-protocol acknowledgement message associated with the first request.

11. The method of claim 10, comprising:

receiving, from the first core, a data response associated with the second request; and

in response to a receipt of the data response from the first core, sending, to the second core, a non-blocking-protocol acknowledgement message associated with the second request.

12. The method of claim 11, comprising:

receiving the non-blocking-protocol invalidation message associated with the second request; and

storing the non-blocking-protocol invalidation message associated with the second request in a memory buffer of the cache logic until a receipt of the non-blocking-protocol acknowledgement message associated with the first request.

13. The method of claim 11, comprising:

in response to a receipt of the non-blocking-protocol acknowledgement message associated with the first request;

processing data included in the received non-blocking-protocol acknowledgement message to generate processed data;

sending a data response including the processed data; and

processing the stored non-blocking-protocol invalidation message to invalidate a local copy of the processed data.

14. The method of claim 8, comprising:

in response to a determination that the second memory request is not in contention with the first memory request, processing the second memory request using a blocking cache coherence protocol.

15. A machine-readable medium having stored thereon data, which if used by at least one machine, causes the at least one machine to fabricate at least one integrated circuit, the at least one integrated circuit to:

receive a first memory request from a first core and a second memory request from a second core;

determine whether the second memory request is in contention with the first memory request for a first memory address stored in a third core; and

in response to a determination that the second memory request is in contention with the first memory request, send a blocking-protocol invalidation message to the third core.

16. The machine-readable medium of claim 15, the at least one integrated circuit to:

send, to the first core, a non-blocking-protocol invalidation message associated with the second request without waiting for a data response from the third core.

17. The machine-readable medium of claim 16, the at least one integrated circuit to:

receive, from the third core, a data response associated with the first request; and

in response to a receipt of the data response from the third core, send, to the first core, a non-blocking-protocol acknowledgement message associated with the first request.

18. The machine-readable medium of claim 17, the at least one integrated circuit to:

receive, from the first core, a data response associated with the second request; and

in response to a receipt of the data response from the first core, send, to the second core, a non-blocking-protocol acknowledgement message associated with the second request.

19. The machine-readable medium of claim 15, the at least one integrated circuit to:

in response to a determination that the second memory request is not in contention with the first memory request, process the second memory request using a blocking cache coherence protocol.

20. The machine-readable medium of claim 15, the at least one integrated circuit comprising a memory buffer to store information about non-blocking-protocol messages being used in a temporary pipeline for parallel memory requests.