Methods and apparatus for reduced overhead data transfer with a shared ring buffer

• US 10,430,352 B1
• Filed: 05/18/2018
• Issued: 10/01/2019
• Est. Priority Date: 05/18/2018
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Sanghi, Karan, Garg, Saurabh, Petkov, Vladislav V.
• Primary Examiner(s): Mamo, Elias
• Application Number:
  US15/984,153
• Time in Patent Office: 501 Days
• Field of Search: None
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0835 for main memory peripheral accesses (e.g. I/O or DMA)
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 15/167 using a common memory, e.g. mailbox
• CPC Class Codes: G06F 15/17375 One dimensional, e.g. linear array, ring
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/154 Networked environment
• CPC Class Codes: G06F 2212/206 Memory mapped I/O

Abstract

Methods and apparatus for reducing bus overhead with virtualized transfer rings. The Inter-Processor Communications (IPC) bus uses a ring buffer (e.g., a so-called Transfer Ring (TR)) to provide Direct Memory Access (DMA)-like memory access between processors. However, performing small transactions within the TR inefficiently uses bus overhead. A Virtualized Transfer Ring (VTR) is a null data structure that doesn'"'"'t require any backing memory allocation. A processor servicing a VTR data transfer includes the data payload as part of an optional header/footer data structure within a completion ring (CR).

Claims

1. A method for requesting a data transfer, comprising:

determining a transfer size associated with a data payload;

and

when the transfer size does not exceed a minimum threshold;

creating a null transfer data structure;

allocating memory for a completion transfer data structure, the completion transfer data structure comprising a dynamically enabled or disabled footer that is sized for the transfer size of the data payload; and

providing the null transfer data structure to the processor, the providing of the null transfer data structure causing transfer of the data payload via the footer of the completion transfer data structure.

2. The method of claim 1, wherein the null transfer data structure comprises multiple null elements.

3. The method of claim 2, wherein the act of providing the null transfer data structure to the processor does not include allocating a backing memory buffer.

4. The method of claim 1, wherein the act of providing the null transfer data structure comprises writing to a doorbell register.

5. The method of claim 1, wherein the minimum threshold comprises eight (8) kilobits (Kb).

6. The method of claim 1, wherein the minimum threshold comprises two (2) kilobits (Kb).

7. The method of claim 1, wherein the completion transfer data structure comprises a completion descriptor.

8. The method of claim 7, wherein the completion descriptor is a data record of a completion descriptor ring.

9. A method for servicing a data transfer, comprising:

retrieving a data structure;

determining a data type of the retrieved data structure;

when the retrieved data structure is a reference data structure, writing a payload to a backing memory identified by the reference data structure; and

otherwise when the retrieved data structure is a null data structure, writing the payload to a footer of a completion data structure, the footer comprising a dynamically enabled or disabled footer that is sized for a payload transfer size that does not exceed a prescribed threshold, and causing transfer of the payload via the footer of the completion data structure.

10. The method of claim 9, wherein the act of retrieving the data structure comprises storing the data structure to a local cache memory that is characterized by a first access latency.

11. The method of claim 10, wherein the backing memory is characterized by a second access latency greater than the first access latency.

12. The method of claim 9, wherein the reference data structure comprises a transfer descriptor of a transfer descriptor ring.

13. The method of claim 9, wherein the completion data structure comprises a completion descriptor of a completion descriptor ring.

14. The method of claim 9, wherein the null data structure comprises a virtual transfer descriptor ring.

20. The method of claim 9, wherein the footer comprises a dynamically enabled or disabled footer that is sized for a payload transfer size that does not exceed two (2) kilobits.

15. A multi-processor apparatus, comprising:

a plurality of processors coupled to a shared non-transitory computer-readable medium;

the shared non-transitory computer-readable medium comprising a transfer data buffer;

logic configured to determine a plurality of transfer sizes associated with a plurality of data payloads; and

logic configured to;

for each of the plurality of data payloads;

when a first data payload has a transfer size that exceeds a minimum threshold size, allocate a memory allocation within the transfer data buffer for the first data payload, provide a transfer descriptor to a first processor of the plurality of processors that identifies the memory allocation; and

otherwise, when the first data payload has a transfer size that does not exceed the minimum threshold size, provide a null transfer descriptor to the first processor of the plurality of processors, wherein the null transfer descriptor is configured to cause the first processor to generate a completion descriptor that includes the first data payload within a dynamically enabled or disabled footer that is sized for the transfer size of the first data payload that does not exceed the minimum threshold size.

16. The multi-processor apparatus of claim 15, wherein the shared non-transitory computer-readable medium is characterized by a first access latency;

the first processor of the plurality of processors is coupled to a local non-transitory computer-readable medium; and

the local non-transitory computer-readable medium is characterized by a second access latency faster than the first access latency.

17. The multi-processor apparatus of claim 16, wherein the first processor of the plurality of processors further comprises logic configured to write the first data payload to the memory allocation.

18. The multi-processor apparatus of claim 15, wherein the first processor of the plurality of processors further comprises logic configured to transmit the completion descriptor that includes the first data payload.

19. The multi-processor apparatus of claim 18, wherein the null transfer descriptor identifies a size of the completion descriptor.