Always-on audio control for mobile device
First Claim
1. An integrated circuit comprising:
- one or more processors;
at least one memory controller; and
a first circuit coupled to the one or more processors and to the memory controller, wherein;
the first circuit is configured to receive audio samples captured by one or more audio input devices and to detect a predetermined pattern in the audio samples during a time that the one or more processors and the memory controller are powered down;
the first circuit is configured to cause the memory controller and the one or more processors to power up responsive to detecting the predetermined pattern, wherein a first delay to initialize the memory controller is less than a second delay to prepare the one or more processors to process the audio samples; and
the first circuit is configured to buffer the audio samples that match the pattern and subsequently-received samples during the first delay, write the audio samples that match the predetermined pattern and subsequently-received samples to memory through the memory controller subsequent to the first delay, and write additional samples received between an end of the first delay and an end of the second delay to the memory through the memory controller.
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Abstract
In an embodiment, an integrated circuit may include one or more CPUs, a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples from a microphone, and match those audio samples against a predetermined pattern to detect a possible command from a user of the device that includes the SOC. In response to detecting the predetermined pattern, the circuit may cause the memory controller to power up so that audio samples may be stored in the memory to which the memory controller is coupled. The circuit may also cause the CPUs to be powered on and initialized, and the operating system (OS) may boot. During the time that the CPUs are initializing and the OS is booting, the circuit and the memory may be capturing the audio samples.
35 Citations
20 Claims
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1. An integrated circuit comprising:
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one or more processors; at least one memory controller; and a first circuit coupled to the one or more processors and to the memory controller, wherein; the first circuit is configured to receive audio samples captured by one or more audio input devices and to detect a predetermined pattern in the audio samples during a time that the one or more processors and the memory controller are powered down; the first circuit is configured to cause the memory controller and the one or more processors to power up responsive to detecting the predetermined pattern, wherein a first delay to initialize the memory controller is less than a second delay to prepare the one or more processors to process the audio samples; and the first circuit is configured to buffer the audio samples that match the pattern and subsequently-received samples during the first delay, write the audio samples that match the predetermined pattern and subsequently-received samples to memory through the memory controller subsequent to the first delay, and write additional samples received between an end of the first delay and an end of the second delay to the memory through the memory controller. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A system comprising:
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an audio input device; an audio coder/decoder (codec) coupled to the audio input device and configured to generate audio samples from sound detected by the audio input device; a memory; and an integrated circuit coupled to the audio codec and the memory, wherein the integrated circuit includes an audio filter, one or more processors, and a memory controller coupled to the memory; the audio filter is configured to detect a predetermined pattern in the audio samples from the audio codec during a time that the memory controller and the one more processors are powered down and is configured to cause the memory controller and the one or more processors to power up responsive to detecting the predetermined pattern, wherein a first delay to initialize the memory controller is less than a second delay to prepare the one or more processors to process the audio samples; and the audio filter is configured to buffer the audio samples that match the pattern and subsequently-received samples during the first delay, write the audio samples that match the predetermined pattern and subsequently-received samples to memory through the memory controller subsequent to the first delay, and write additional samples received between an end of the first delay and an end of the second delay to the memory through the memory controller. - View Dependent Claims (13, 14, 15, 16)
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17. A method comprising:
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during a time that the one or more processors and a memory controller in an integrated circuit are powered down, monitoring audio samples in a first circuit within the integrated circuit that remains powered; detecting a predetermined pattern in the audio samples in the first circuit; requesting power up of the memory controller and the one or more processors in response to the detecting, wherein a first delay to initialize the memory controller is less than a second delay to prepare the one or more processors to process the audio samples; buffering the audio samples and subsequently-received audio samples in a buffer in the first circuit during the first delay; writing the audio samples that match the predetermined pattern and subsequently-received samples to memory through the memory controller subsequent to the first delay; and writing additional samples received between an end of the first delay and an end of the second delay to the memory through the memory controller. - View Dependent Claims (18, 19, 20)
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Specification