Systems and methods for maintaining refresh operations of memory banks using a shared address path

• US 10,431,288 B2
• Filed: 11/15/2018
• Issued: 10/01/2019
• Est. Priority Date: 11/01/2017
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Lee, Joosang
• Primary Examiner(s): Byrne, Harry W
• Application Number:
  US16/192,389
• Publication Number:
  US 20190130963A1
• Time in Patent Office: 320 Days
• Field of Search: 36518525
• CPC Class Codes: G11C 11/40603 Arbitration, priority and concurrent access to memory cells for read/write or refresh operations
• CPC Class Codes: G11C 11/40618 Refresh operations over multiple banks or interleaving
• CPC Class Codes: G11C 11/4082 Address Buffers; level conversion circuits
• CPC Class Codes: G11C 2211/4063 Interleaved refresh operations

Abstract

A memory device includes memory banks that each has multiple rows with row addresses. The memory device also includes a counter that stores and increments a first row address of a first row of a first set of memory banks to a second row address of a second row of the first set of memory banks in response to a first refresh operation when the memory device is operating in a first mode. The memory device further includes circuitry that blocks incrementing the second row address to a third row address of a third row of the first set of memory banks when the memory device transitions from the first mode to a second mode and the first refresh operation is not paired with a second refresh operation that is performed when the memory device is operating in the first mode.

Claims

1. A method comprising:

receiving an instruction to refresh a row address stored in a counter of a memory device;

blocking incrementing the row address when the memory device transitioned from a first mode of operation to a second mode of operation and an immediately previous refresh operation was unpaired;

incrementing the row address stored in the counter when the memory device did not transition from the first mode of operation to the second mode of operation, or the memory device transitioned from the first mode of operation to the second mode of operation and the immediately previous refresh operation was paired; and

refreshing the row address stored in the counter.

2. The method of claim 1, wherein the method comprises determining whether the immediately previous refresh operation was unpaired based at least in part on the least significant bit of a second row address associated with the immediately previous refresh operation.

3. The method of claim 1, wherein the first mode of operation is configured to enable a refresh command to perform a refresh operation on one or more rows of a plurality of rows of the memory device.

4. The method of claim 1, wherein the second mode of operation is configured to enable a refresh command to perform two refresh operations on two sets of rows of a plurality of rows of the memory device.

5. The method of claim 1, wherein the first mode of operation comprises an FGR 2×

mode.

6. The method of claim 1, wherein the first mode of operation comprises an auto-refresh mode.

7. The method of claim 1, wherein the second mode of operation comprises an FGR 1×

mode.

8. The method of claim 1, wherein the second mode of operation comprises a self-refresh mode.

9. The method of claim 1, comprising determining whether the immediately previous refresh operation was unpaired based on the least significant bit of the row address.