Parasitic capacitance compensation circuit

• US 10,431,424 B2
• Filed: 12/06/2018
• Issued: 10/01/2019
• Est. Priority Date: 02/18/2015
• Status: Active Grant

• Current Assignee: ASM America Incorporated (ASM International NV)
• Original Assignee: Reno Technologies Inc.
• Inventors: Mavretic, Anton, Costanzo, Ian M.
• Primary Examiner(s): Jones, Stephen E.
• Assistant Examiner(s): Outten, Samuel S
• Application Number:
  US16/211,961
• Publication Number:
  US 20190115191A1
• Time in Patent Office: 299 Days
• Field of Search: 333 32
• CPC Class Codes: H01J 2237/334 Etching
• CPC Class Codes: H01J 37/32082 Radio frequency generated discharge H01J37/32357, H01J37/32366, H01J37/32394 and H01J37/32403 take precedence
• CPC Class Codes: H01J 37/32174 Circuits specially adapted for controlling the RF discharge
• CPC Class Codes: H01J 37/32183 Matching circuits
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H02M 1/088 for the simultaneous control of series or parallel connected semiconductor devices
• CPC Class Codes: H02M 3/01 Resonant DC/DC converters
• CPC Class Codes: H02M 3/33569 having several active switching elements H02M3/3353 takes precedence
• CPC Class Codes: H03H 7/38 Impedance-matching networks
• CPC Class Codes: H03H 7/40 Automatic matching of load impedance to source impedance
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 17/122 in field-effect transistor switches
• CPC Class Codes: H03K 17/687 : the devices being field-effect transistors
• CPC Class Codes: H03K 17/691 : using transformer coupling
• CPC Class Codes: H03K 17/7955 : using phototransistors
• CPC Class Codes: H03K 2017/6875 : using self-conductive, depletion FETs
• CPC Class Codes: H04B 1/44 : Transmit/receive switching

Abstract

In one embodiment, a parasitic capacitance compensation circuit for a switch is disclosed that includes a first inductor operably coupled between a first terminal and a second terminal, and a second inductor operably coupled between the first and second terminals and parallel to the first inductor. The second inductor is switched in when a peak voltage on the first and second terminals falls below a first voltage. The first inductance tunes out substantially all of a parasitic capacitance of the switch when the switch is OFF and the peak voltage is above the first voltage. The first and second inductances collectively tune out substantially all of the parasitic capacitance of the switch when the switch is OFF and the peak voltage is below the first voltage.

Claims

1. A parasitic capacitance compensation circuit for a switch, the circuit comprising:

a first inductor operably coupled between a first terminal and a second terminal, the first inductor causing a first inductance between the first and second terminals, the first and second terminals configured to be operably coupled, respectively, to first and second terminals of the switch; and

a second inductor operably coupled between the first and second terminals and parallel to the first inductor, the second inductor causing a second inductance between the first and second terminals of the switch when the second inductor is switched in, the second inductor being switched in when a peak voltage on the first and second terminals falls below a first voltage;

wherein the first inductance tunes out substantially all of a parasitic capacitance of the switch when the switch is OFF and the peak voltage is above the first voltage; and

wherein the first and second inductances collectively tune out substantially all of the parasitic capacitance of the switch when the switch is OFF and the peak voltage is below the first voltage.

2. The circuit of claim 1 wherein the second inductor is switched in by a first sub-switch positioned in series with the second inductor.

3. The circuit of claim 2 wherein the first sub-switch is switched ON when the peak voltage on the first terminal falls below the first voltage.

4. The circuit of claim 3 wherein:

a voltage divider is operably coupled to the first and second terminals and configured to sample the peak voltage; and

a transformer is operably coupled to the voltage divider and the sub-switch, and the transformer is configured to keep the sub-switch OFF when the peak voltage is not below the first voltage.

5. The circuit of claim 1 wherein the first voltage is a peak voltage on the first and second terminals when an output capacitance on the switch substantially doubles from an output capacitance on the switch when a most typical peak voltage is on the first and second terminals.

6. The circuit of claim 1 wherein the first inductance resonates the parasitic capacitance of the switch when the switch is OFF and the peak voltage is at a most typical peak voltage for the switch.

7. A semiconductor processing tool comprising:

a plasma chamber configured to deposit a material onto a substrate or etch a material from the substrate; and

an impedance matching circuit operably coupled to the plasma chamber, matching circuit comprising;

an RF input configured to be operably coupled to an RF source;

an RF output operably coupled to the plasma chamber; and

an electronically variable capacitor (EVC), the EVC comprising discrete capacitors, each discrete capacitor having a corresponding switch for switching in and out the discrete capacitor, each corresponding switch comprising a parasitic capacitance compensation circuit comprising;

a first inductor operably coupled between a first terminal and a second terminal of the corresponding switch, the first inductor causing a first inductance between the first and second terminals, the first and second terminals configured to be operably coupled, respectively, to first and second terminals of the switch; and

a second inductor operably coupled between the first and second terminals and parallel to the first inductor, the second inductor causing a second inductance between the first and second terminals of the switch when the second inductor is switched in, the second inductor being switched in when a peak voltage on the first and second terminals falls below a first voltage;

wherein the first inductance tunes out substantially all of a parasitic capacitance of the switch when the switch is OFF and the peak voltage is above the first voltage; and

wherein the first and second inductances collectively tune out substantially all of the parasitic capacitance of the switch when the switch is OFF and the peak voltage is below the first voltage.

8. The processing tool of claim 7 wherein the second inductor is switched in by a first sub-switch positioned in series with the second inductor.

9. The processing tool of claim 8 wherein the first sub-switch is switched ON when the peak voltage on the first terminal falls below the first voltage.

10. The processing tool of claim 9 further comprising:

a voltage divider (Cc1, Cc2) is operably coupled to the first and second terminals and configured to sample the peak voltage;

a transformer is operably coupled to the voltage divider and the sub-switch, and the transformer is configured to keep the sub-switch OFF when the peak voltage is not below the first voltage.

11. The processing tool of claim 7 wherein the first voltage is a peak voltage on the first and second terminals when an output capacitance on the switch substantially doubles from an output capacitance on the switch when a most typical peak voltage is on the first and second terminals.

12. The processing tool of claim 7 wherein the first inductance resonates the parasitic capacitance of the switch when the switch is OFF and the peak voltage is at a most typical peak voltage for the switch.

13. A method of compensating for parasitic capacitance for a switch, the method comprising:

operably coupling a first inductor between a first terminal and a second terminal, the first inductor causing a first inductance between the first and second terminals, the first and second terminals configured to be operably coupled, respectively, to first and second terminals of the switch;

operably coupling a second inductor between the first and second terminals and parallel to the first inductor, the second inductor causing a second inductance between the first and second terminals of the switch when the second inductor is switched in; and

switching in the second inductor when a peak voltage on the first and second terminals falls below a first voltage;

wherein the first inductance tunes out substantially all of a parasitic capacitance of the switch when the switch is OFF and the peak voltage is above the first voltage; and

wherein the first and second inductances collectively tune out substantially all of the parasitic capacitance of the switch when the switch is OFF and the peak voltage is below the first voltage.

14. The method of claim 13 wherein the first voltage is a peak voltage on the first and second terminals when an output capacitance on the switch substantially doubles from an output capacitance on the switch when a most typical peak voltage is on the first and second terminals.

15. The method of claim 14 wherein first inductance is 1.9H.

16. The method of claim 15 wherein second inductance is 2.1H.

17. The method of claim 13 wherein the second inductor is switched in by a first sub-switch positioned in series with the second inductor.

18. The method of claim 17 wherein the first sub-switch is switched ON when the peak voltage on the first terminal falls below the first voltage.

19. The method of claim 18 further comprising:

operably coupling a voltage divider (Cc1, Cc2) to the first and second terminals that is configured to sample the peak voltage; and

operably coupling a transformer to the voltage divider and the sub-switch, and the transformer is configured to keep the sub-switch OFF when the peak voltage is not below the first voltage.

20. The method of claim 13 wherein the first inductance resonates the parasitic capacitance of the switch when the switch is OFF and the peak voltage is at a most typical peak voltage for the switch.

21. A method of fabricating a semiconductor, the method comprising:

placing a substrate in a plasma chamber configured to deposit a material layer onto the substrate or etch a material layer from the substrate;

energizing plasma within the plasma chamber by coupling RF power from an RF source into the plasma chamber to perform a deposition or etching; and

while energizing the plasma, carrying out an impedance match by an impedance matching network coupled between a load and an RF source, wherein the impedance matching network comprises;

an RF input configured to operably couple to the RF source;

an RF output configured to operably couple to the plasma chamber; and

an electronically variable capacitor (EVC), the EVC comprising discrete capacitors, each discrete capacitor having a corresponding switch for switching in and out the discrete capacitor, each corresponding switch comprising a parasitic capacitance compensation circuit comprising;

a first inductor operably coupled between a first terminal and a second terminal of the corresponding switch, the first inductor causing a first inductance between the first and second terminals, the first and second terminals configured to be operably coupled, respectively, to first and second terminals of the switch; and

a second inductor operably coupled between the first and second terminals and parallel to the first inductor, the second inductor causing a second inductance between the first and second terminals of the switch when the second inductor is switched in, the second inductor being switched in when a peak voltage on the first and second terminals falls below a first voltage;

wherein the first inductance tunes out substantially all of a parasitic capacitance of the switch when the switch is OFF and the peak voltage is above the first voltage; and

wherein the first and second inductances collectively tune out substantially all of the parasitic capacitance of the switch when the switch is OFF and the peak voltage is below the first voltage.