Semiconductor devices and fabrication methods thereof

• US 10,431,498 B2
• Filed: 05/04/2018
• Issued: 10/01/2019
• Est. Priority Date: 05/05/2017
• Status: Active Grant

• Current Assignee: Semiconductor Manufacturing International Corporation
• Original Assignee: Semiconductor Manufacturing International (Shanghai) Corporation (Semiconductor Manufacturing International Corporation)
• Inventors: Zhou, Fei
• Primary Examiner(s): Yushin, Nikolay K
• Application Number:
  US15/971,002
• Publication Number:
  US 20180323107A1
• Time in Patent Office: 515 Days
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66795 : with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 : the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method for fabricating a semiconductor structure includes forming a plurality of gate structures on the base substrate with each gate structure including a gate electrode and sidewall spacers on each aide surface of the gate electrode, forming source/drain doped regions in the base substrate on opposite sides of each gate structure, forming a sacrificial layer on side surfaces of each sidewall spacer, and performing a pre-amorphous ion implantation process on the source/drain doped regions using the sacrificial layer as a mask.

Claims

1. A method for fabricating a semiconductor structure, comprising:

forming a plurality of gate structures on the base substrate, wherein each gate structure includes a gate electrode and sidewall spacers on each side surface of the gate electrode;

forming source/drain doped regions in the base substrate on opposite sides of each gate structure;

forming a sacrificial layer on side surfaces of each sidewall spacer; and

performing a pre-amorphous ion implantation process on the source/drain doped regions using the sacrificial layer as a mask, wherein each of the source/drain doped regions is divided, in a direction perpendicular to a top surface of the substrate and an extension direction of the gate structures, into a first portion directly covered by the sacrificial layer and an amorphous layer exposed by the sacrificial layer.

2. The method for fabricating the semiconductor structure according to claim 1, wherein:

the sacrificial layer is made of at least one of SiO₂, SiC, and SiON.

3. The method for fabricating the semiconductor structure according to claim 1, wherein:

the gate electrode includes a metal gate electrode.

4. The method for fabricating the semiconductor structure according to claim 1, wherein:

the gate electrode is a polycrystalline silicon gate electrode.

5. The method for fabricating the semiconductor structure according to claim 1, after performing the pre-amorphous ion implantation process on the source/drain doped regions, further including:

forming a conductive plug on each of the source/drain doped regions to electrically connect to each of the source/drain doped regions.

6. The method for fabricating the semiconductor structure according to claim 1, wherein the base substrate includes a substrate and a plurality of fin structures, and:

the plurality of gate structures are formed across the fin structures; and

the source/drain doped regions are formed in a corresponding fin structure on the opposite sides of each gate structure.

7. The method for fabricating the semiconductor structure according to claim 1, wherein:

each of the source/drain doped regions is divided by a plane parallel to each side surface of the gate electrode and tangent to sidewalls of the sacrificial layer to two regions adjacent to each other, and

ions doped into the source/drain doped regions during the pre-amorphous ion implantation process include at least one of C ions, Ge ions, and Si ions.

8. The method for fabricating the semiconductor structure according to claim 7, wherein parameters used in the pre-amorphous ion implantation process include:

an implantation energy in a range of approximately 5 keV to 20 keV;

an implantation dose in a range of approximately 4.0E13 atom/cm² to 2.3E15 atom/cm².

9. The method for fabricating the semiconductor structure according to claim 1, after forming the source/drain doped regions and prior to forming the sacrificial layer, further including:

forming an etch stop layer on the base substrate as well as top and side surfaces of the gate structures.

10. The method for fabricating the semiconductor structure according to claim 9, wherein:

the etch stop layer and the sacrificial layer are made of different materials.

11. The method for fabricating the semiconductor structure according to claim 1, wherein:

a thickness of the sacrificial layer is in a range of approximately 30 Å

to 150 Å

.

12. The method for fabricating the semiconductor structure according to claim 3, wherein forming the sacrificial layer includes:

forming a sacrificial film on the base substrate as well as top and side surfaces of the gate structures;

forming a hard mask layer on the sacrificial film to expose a portion of the sacrificial film formed on the base substrate and top surfaces of the gate structures; and

removing the portion of the sacrificial film formed on the base substrate and the top surfaces of the gate structures to form the sacrificial layer using the hard mask layer as an etch mask.

13. The method for fabricating the semiconductor structure according to claim 12, wherein:

the sacrificial film is formed by a chemical vapor deposition process.

14. The method for fabricating the semiconductor structure according to claim 12, wherein:

the portion of the sacrificial film formed on the base substrate and the top surfaces of the gate structures is removed by a dry etching process.

15. A semiconductor structure, comprising:

a base substrate;

a plurality of gate structures formed on the base substrate, wherein each gate structure includes a gate electrode and sidewall spacers on each side surface of the gate electrode;

a sacrificial layer formed on the sidewall spacers on each side surface of the gate electrode; and

source/drain doped regions formed in the base substrate on opposite sides of each gate structure, wherein

each of the source/drain doped regions includes an amorphous layer exposed by the sacrificial layer from an ion implantation using the sacrificial layer as a mask and a remaining portion of each of the source/drain doped regions directly covered by the sacrificial layer, and

the amorphous layer and the remaining portion of each of the source/drain doped regions are divided, in a direction perpendicular to a top surface of the substrate and an extension direction of the gate structures.

16. The semiconductor structure according to claim 15, wherein:

the sacrificial layer is made of at least one of SiO₂, SiC, and SiON.

17. The semiconductor structure according to claim 15, wherein:

a thickness of the sacrificial layer is in a range of approximately 30 Å

to 150 Å

.

18. The semiconductor structure according to claim 15, wherein:

the source/drain doped regions are doped by ions including at least one of C ions, Ge ions, and Si ions.

19. The semiconductor structure according to claim 15, further including:

a conductive plug formed on each of the source/drain doped regions to electrically connect to each of the source/drain doped regions.

20. The semiconductor structure according to claim 15, wherein the base substrate includes a substrate and a plurality of fin structures, and

the plurality of gate structures are formed across the fin structures;

and

the source/drain doped regions are formed in a corresponding fin structure on the opposite sides of each gate structure.