Semiconductor devices and fabrication methods thereof
First Claim
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1. A method for fabricating a semiconductor structure, comprising:
- forming a plurality of gate structures on the base substrate, wherein each gate structure includes a gate electrode and sidewall spacers on each side surface of the gate electrode;
forming source/drain doped regions in the base substrate on opposite sides of each gate structure;
forming a sacrificial layer on side surfaces of each sidewall spacer; and
performing a pre-amorphous ion implantation process on the source/drain doped regions using the sacrificial layer as a mask, wherein each of the source/drain doped regions is divided, in a direction perpendicular to a top surface of the substrate and an extension direction of the gate structures, into a first portion directly covered by the sacrificial layer and an amorphous layer exposed by the sacrificial layer.
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Abstract
A method for fabricating a semiconductor structure includes forming a plurality of gate structures on the base substrate with each gate structure including a gate electrode and sidewall spacers on each aide surface of the gate electrode, forming source/drain doped regions in the base substrate on opposite sides of each gate structure, forming a sacrificial layer on side surfaces of each sidewall spacer, and performing a pre-amorphous ion implantation process on the source/drain doped regions using the sacrificial layer as a mask.
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20 Claims
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1. A method for fabricating a semiconductor structure, comprising:
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forming a plurality of gate structures on the base substrate, wherein each gate structure includes a gate electrode and sidewall spacers on each side surface of the gate electrode; forming source/drain doped regions in the base substrate on opposite sides of each gate structure; forming a sacrificial layer on side surfaces of each sidewall spacer; and performing a pre-amorphous ion implantation process on the source/drain doped regions using the sacrificial layer as a mask, wherein each of the source/drain doped regions is divided, in a direction perpendicular to a top surface of the substrate and an extension direction of the gate structures, into a first portion directly covered by the sacrificial layer and an amorphous layer exposed by the sacrificial layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A semiconductor structure, comprising:
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a base substrate; a plurality of gate structures formed on the base substrate, wherein each gate structure includes a gate electrode and sidewall spacers on each side surface of the gate electrode; a sacrificial layer formed on the sidewall spacers on each side surface of the gate electrode; and source/drain doped regions formed in the base substrate on opposite sides of each gate structure, wherein each of the source/drain doped regions includes an amorphous layer exposed by the sacrificial layer from an ion implantation using the sacrificial layer as a mask and a remaining portion of each of the source/drain doped regions directly covered by the sacrificial layer, and the amorphous layer and the remaining portion of each of the source/drain doped regions are divided, in a direction perpendicular to a top surface of the substrate and an extension direction of the gate structures. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification