Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices

• US 10,431,513 B2
• Filed: 05/01/2017
• Issued: 10/01/2019
• Est. Priority Date: 08/19/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ye, Seng Kim Dalson, Chong, Chin Hui, Lee, Choon Kuan, Lee, Wang Lai, Said, Roslan Bin
• Primary Examiner(s): Wilczewski, Mary A
• Application Number:
  US15/583,826
• Publication Number:
  US 20170301598A1
• Time in Patent Office: 883 Days
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/06136 Covering only the central area of the surface to be connected, i.e. central arrangements
• CPC Class Codes: H01L 2224/16055 being circular or elliptic
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73257 Bump and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/92147 the second connecting process involving a wire connector
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/1023 : the support being an insulating substrate
• CPC Class Codes: H01L 2225/1041 : Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/1088 : Arrangements to limit the height of the assembly
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49833 : the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/00 : Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereofdevices consisting of a plurality of solid state components formed in or on a common substrate H01L27/00; photovoltaic modules or arrays of photovoltaic cells H01L31/042 ; panels or arrays of photo electrochemical cells H01G9/2068
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/117 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/0102 : Calcium [Ca]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01052 : Tellurium [Te]
• CPC Class Codes: H01L 2924/0106 : Neodymium [Nd]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15184 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices are described herein. In one embodiment, a set of stacked microelectronic devices includes (a) a first microelectronic die having a first side and a second side opposite the first side, (b) a first substrate attached to the first side of the first microelectronic die and electrically coupled to the first microelectronic die, (c) a second substrate attached to the second side of the first microelectronic die, (d) a plurality of electrical couplers attached to the second substrate, (e) a third substrate coupled to the electrical couplers, and (f) a second microelectronic die attached to the third substrate. The electrical couplers are positioned such that at least some of the electrical couplers are inboard the first microelectronic die.

Claims

1. A stacked microelectronic device, comprising:

a first microelectronic device, including;

a first lower substrate with a footprint,

a first microelectronic die carried on the first lower substrate and electrically coupled to the first lower substrate, and

a first upper substrate disposed over the first microelectronic die and electrically coupled to the first lower substrate,

wherein the first microelectronic die includes a first perimeter array of bond-pads on an upper side thereof, and wherein the first upper substrate is positioned inboard of the first perimeter array; and

a second microelectronic device disposed over the first microelectronic device, the second microelectronic device including;

a second lower substrate with the footprint,

a second microelectronic die carried on the second lower substrate and electrically coupled to the second lower substrate, and

a second upper substrate disposed over the second microelectronic die and electrically coupled to the second lower substrate,

wherein the second microelectronic die includes a second perimeter array of bond-pads on an upper side thereof, and wherein the second upper substrate is positioned inboard of the second perimeter array;

wherein the second lower substrate is electrically coupled to the first upper substrate.

2. The stacked microelectronic device of claim 1 wherein the first microelectronic device further includes a first casing at least partially encapsulating a sidewall of the first microelectronic die.

3. The stacked microelectronic device of claim 1 wherein the second microelectronic device further includes a second casing at least partially encapsulating a sidewall of the second microelectronic die.

4. The stacked microelectronic device of claim 1 wherein the first microelectronic die is electrically coupled to the first lower substrate by a first plurality of wirebonds.

5. The stacked microelectronic device of claim 4 wherein the first upper substrate is electrically coupled to the first lower substrate by a second plurality of wirebonds.

6. The stacked microelectronic device of claim 5, wherein the first microelectronic device further includes a first encapsulation encapsulating the first and second pluralities of wirebonds.

7. The stacked microelectronic device of claim 1 wherein the second microelectronic die is electrically coupled to the second lower substrate by a third plurality of wirebonds.

8. The stacked microelectronic device of claim 7 wherein the second upper substrate is electrically coupled to the second lower substrate by a fourth plurality of wirebonds.

9. The stacked microelectronic device of claim 8, wherein the second microelectronic device further includes a second encapsulation encapsulating the third and fourth pluralities of wirebonds.

10. The stacked microelectronic device of claim 1 wherein the second lower substrate is electrically coupled to the first upper substrate by a plurality of solder connections.

11. The stacked microelectronic device of claim 1, further comprising:

a third microelectronic device disposed over the second microelectronic device, the third microelectronic device including;

a third lower substrate,

a third microelectronic die carried on the third lower substrate and electrically coupled to the third lower substrate, and

a third upper substrate disposed over the third microelectronic die and electrically coupled to the third lower substrate;

wherein the third lower substrate is electrically coupled to the second upper substrate.

12. A stacked microelectronic device, comprising:

a first microelectronic device, including;

a first lower substrate with a footprint,

a first microelectronic die carried on the first lower substrate and electrically coupled to the first lower substrate by a first plurality of wirebonds, and

a first upper substrate disposed over the first microelectronic die and electrically coupled to the first lower substrate by a second plurality of wirebonds,

wherein the first microelectronic die includes a first perimeter array of bond-pads on an upper side thereof, and wherein the first upper substrate is positioned inboard of the first perimeter array; and

a second microelectronic device disposed over the first microelectronic device, the second microelectronic device including;

a second lower substrate with the footprint,

a second microelectronic die carried on the second lower substrate and electrically coupled to the second lower substrate by a third plurality of wirebonds, and

a second upper substrate disposed over the second microelectronic die and electrically coupled to the second lower substrate by a fourth plurality of wirebonds,

wherein the second microelectronic die includes a second perimeter array of bond-pads on an upper side thereof, and wherein the second upper substrate is positioned inboard of the second perimeter array;

wherein the second lower substrate is electrically coupled to the first upper substrate by a plurality of solder connections.

13. The stacked microelectronic device of claim 12 wherein the first plurality of wirebonds are attached to the first perimeter array of bond-pads.

14. The stacked microelectronic device of claim 12 wherein the third plurality of wirebonds are attached to the second perimeter array of bond-pads.