Semiconductor package

• US 10,431,547 B2
• Filed: 01/13/2018
• Issued: 10/01/2019
• Est. Priority Date: 07/05/2017
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Nam, Geol, Kim, Young Lyong
• Primary Examiner(s): Trinh, Hoa B
• Application Number:
  US15/870,910
• Publication Number:
  US 20190013272A1
• Time in Patent Office: 626 Days
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06544 Design considerations for via connections, e.g. geometry or layout
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

A semiconductor package is provided including a package substrate, a first semiconductor chip on the substrate, with a first surface and a second surface opposite to each other; a plurality of first connection terminals disposed on the first surface contacting an upper surface of the substrate; a second semiconductor chip disposed on the second surface, with a third surface and a fourth surface opposite to each other; a plurality of second connection terminals disposed on the third surface contacting the second surface, wherein an absolute value between a first area, the sum of areas in which the plurality of first connection terminals contact the upper surface of the package substrate, and a second area, the sum of areas in which the plurality of second connection terminals contact the second surface of the first semiconductor chip, is equal to or less than about 0.3 of the first area.

Claims

1. A semiconductor package comprising:

a package substrate;

a first semiconductor chip disposed on the package substrate, the first semiconductor chip including a first surface and a second surface opposite to each other;

a plurality of first connection terminals disposed on the first surface of the first semiconductor chip and in contact with an upper surface of the package substrate;

a second semiconductor chip overlying the second surface of the first semiconductor chip, the second semiconductor chip including a third surface and a fourth surface opposite to each other; and

a plurality of second connection terminals disposed on the third surface of the second semiconductor chip and in contact with the second surface of the first semiconductor chip,

wherein an absolute value between a first area which is a sum of areas in which the plurality of first connection terminals contact the upper surface of the package substrate and a second area which is a sum of areas in which the plurality of second connection terminals contact the second surface of the first semiconductor chip is equal to or less than about 0.3 of the first area.

2. The semiconductor package of claim 1, wherein a total number of the plurality of first connection terminals and a total number of the plurality of second connection terminals are different from each other.

3. The semiconductor package of claim 2, wherein the total number of the plurality of second connection terminals is larger than the total number of the plurality of first connection terminals.

4. The semiconductor package of claim 1, wherein the first semiconductor chip comprises a first via passing therethrough,

wherein the plurality of first connection terminals comprises a first signal connection terminal electrically connected to the first via, and a first dummy connection terminal spaced apart from the first signal connection terminal, and

wherein the plurality of second connection terminals comprises a second signal connection terminal electrically connected to the first via, and second and third dummy connection terminals spaced apart from the second signal connection terminal.

5. The semiconductor package of claim 4, wherein the first, second and third dummy connection terminals are not electrically connected to the first via.

6. The semiconductor package of claim 4, wherein at least a portion of the first dummy connection terminals vertically overlaps at least a portion of the second dummy connection terminals, and

wherein the first dummy connection terminals do not vertically overlap the third dummy connection terminals.

7. The semiconductor package of claim 4, wherein the package substrate comprises an external connection terminal disposed on a lower surface of the package substrate, and a substrate pad disposed on an upper surface of the package substrate and connected to the external connection terminal,

wherein the first signal connection terminal is electrically connected to the substrate pad, and

wherein the first dummy connection terminal is not electrically connected to the substrate pad.

8. The semiconductor package of claim 1, wherein each of the plurality of first connection terminals comprises a first bump, and a first pad disposed between the first bump and the first surface of the first semiconductor chip, and

wherein the first area is a value measured at a boundary in which the first bump contacts the upper surface of the package substrate.

9. The semiconductor package of claim 8, wherein each of the plurality of second connection terminals comprises a second bump, and a second pad disposed between the second bump and the third surface of the second semiconductor chip, and

wherein the second area is a value measured at a boundary in which the second bump contacts the second surface of the first semiconductor chip.

10. The semiconductor package of claim 1, further comprising:

a third semiconductor chip disposed on the fourth surface of the second semiconductor chip, and includes a fifth surface and a sixth surface opposite to each other; and

a plurality of third connection terminals disposed on the fifth surface of the third semiconductor chip and contact the fourth surface of the second semiconductor chip.

11. The semiconductor package of claim 10, wherein an absolute value of a difference between the first area and a third area is about 0.3 or less of the first area, the third area being a sum of areas in which the plurality of third connection terminals contact the fourth surface of the second semiconductor chip.

12. The semiconductor package of claim 10, wherein the second semiconductor chip comprises a second via passing therethrough,

wherein the plurality of third connection terminals comprises a third signal connection terminal electrically connected to the second via, and a fourth dummy connection terminal spaced apart from the third signal connection terminal, and

wherein the fourth dummy connection terminal is not electrically connected to the second via.

13. A semiconductor package comprising:

a package substrate;

a first semiconductor chip disposed on a package substrate, the first semiconductor chip including a first surface and a second surface opposite to each other;

a first signal connection terminal disposed between the first surface of the first semiconductor chip and an upper surface of the package substrate, the first signal connection terminal electrically connecting the first semiconductor chip and the package substrate;

a first dummy connection terminal interposed between the first surface of the first semiconductor chip and the upper surface of the package substrate, the first dummy connection terminal spaced apart from the first signal connection terminal;

a second semiconductor chip overlying the second surface of the first semiconductor chip, the second semiconductor chip including a third surface and a fourth surface opposite to each other;

a second signal connection terminal disposed between the third surface of the second semiconductor chip and the second surface of the first semiconductor chip, the second signal connection terminal electrically connecting the first semiconductor chip and the second semiconductor chip; and

a second dummy connection terminal and a third dummy connection terminal which are disposed between the third surface of the second semiconductor chip and the second surface of the first semiconductor chip, the second dummy connection terminal and the third dummy connection terminal spaced apart from the second signal connection terminal,

wherein at least a portion of the first dummy connection terminal and at least a portion of the second dummy connection terminal vertically overlap each other, and the first dummy connection terminal and the third dummy connection terminals does not vertically overlap each other;

wherein a first area is a sum of an area in which the first signal connection terminal contacts the upper surface of the package substrate, and an area in which the first dummy connection terminal contacts the upper surface of the package substrate,

wherein a second area is a sum of an area in which the second signal connection terminal contacts the second surface of the first semiconductor chip, an area in which the second dummy connection terminal contacts the second surface of the first semiconductor chip, and an area in which the third dummy connection terminal contacts the second surface of the first semiconductor chip,

wherein the first area and the second area are different each other, and

wherein an absolute value of a difference between the first area and the second area is about 0.3 or less of the first area.

14. The semiconductor package of claim 13, wherein the first dummy connection terminal does not electrically connect the package substrate and the first semiconductor chip, and

wherein the second and third dummy connection terminals do not electrically connect the first semiconductor chip and the second semiconductor chip.

15. The semiconductor package of claim 13, further comprising:

a third semiconductor chip overlying the fourth surface of the second semiconductor chip, the third semiconductor chip including a fifth surface and a sixth surface opposite to each other;

a third signal connection terminal interposed between the fifth surface of the third semiconductor chip and the fourth surface of the second semiconductor chip, the third signal connection terminal electrically connecting the second semiconductor chip and the third semiconductor chip; and

a fourth dummy connection terminal interposed between the fifth surface of the third semiconductor chip and the fourth surface of the second semiconductor chip, and spaced apart from the third signal connection terminal.

16. The semiconductor package of claim 15,

wherein a third area is a sum of an area in which the third signal connection terminal contacts the fourth surface of the second semiconductor chip, and an area in which the fourth dummy connection terminal contacts the fourth surface of the second semiconductor chip, and

wherein an absolute value of a difference between the first area and the third area is about 0.3 or less of the first area.

17. A semiconductor package comprising:

a package substrate including a substrate pad on an upper surface thereof;

a first signal connection terminal electrically connected to the substrate pad;

a first dummy connection terminal spaced apart from the substrate pad and the first signal connection terminal and disposed on the package substrate;

a first semiconductor chip disposed on the first dummy connection terminal and the first signal connection terminal, the first semiconductor chip including a first via electrically connected to the first signal connection terminal;

a second signal connection terminal connected to the first via and overlying the first semiconductor chip;

a second dummy connection terminal spaced apart from the first via and the second signal connection terminal and overlying the first semiconductor chip; and

a plurality of second semiconductor chips sequentially stacked on the second dummy connection terminal and the second signal connection terminal, each of the plurality of second semiconductor chips being electrically connected through a second via penetrating each of the plurality of second semiconductor chips,

wherein a first area is a sum of an area in which the first signal connection terminal contacts the upper surface of the package substrate, and an area in which the first dummy connection terminal contacts the upper surface of the package substrate,

wherein a second area is a sum of an area in which the second signal connection terminal contacts the first semiconductor chip, and an area in which the second dummy connection terminal contacts the first semiconductor chip, and

wherein an absolute value of a difference between the first area and the second area is about 0.3 or less of the first area.

18. The semiconductor package of claim 17, wherein the first semiconductor chip comprises a first pad disposed on an upper surface thereof and in contact with the second signal connection terminal, and a second pad disposed on the upper surface of the first semiconductor chip and in contact with the second dummy connection terminal, and

wherein the second area is a value measured at a boundary in which the first pad and the second signal connection terminal are in contact with each other and a boundary in which the second pad and the second dummy connection terminal are in contact with each other.

19. The semiconductor package of claim 17, wherein the first dummy connection terminal does not electrically connect the first semiconductor chip and the package substrate, and

wherein the second dummy connection terminal does not electrically connect the first semiconductor chip and the plurality of second semiconductor chips.