Method for stacking core and uncore dies having landing slots

• US 10,431,573 B2
• Filed: 12/06/2016
• Issued: 10/01/2019
• Est. Priority Date: 09/26/2014
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Rusu, Stefan
• Primary Examiner(s): Everhart, Caridad
• Application Number:
  US15/370,904
• Publication Number:
  US 20170084593A1
• Time in Patent Office: 1,029 Days
• CPC Class Codes: G06F 12/1045 associated with a data cache
• CPC Class Codes: G06F 15/76 Architectures of general purpose stored program computers with program plugboard G06F15/08; multicomputers G06F15/16
• CPC Class Codes: G06F 2212/1008 Correctness of operation, e.g. memory ordering
• CPC Class Codes: G06F 2212/283 Plural cache memories
• CPC Class Codes: G06F 2212/455 Image or video data
• CPC Class Codes: G06F 2212/608 Details relating to cache mapping
• CPC Class Codes: G06F 2212/68 Details of translation look-aside buffer [TLB]
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06593 Mounting aids permanently on device; arrangements for alignment use of temporary supports H01L21/6835
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method is described for stacking a plurality of cores. For example, one embodiment comprises: mounting an uncore die on a package, the uncore die comprising a plurality of exposed landing slots, each landing slot including an inter-die interface usable to connect vertically to a cores die, the uncore die including a plurality of uncore components usable by cores within the cores die; and vertically coupling a first cores die comprising a first plurality of cores on top of the uncore die, the cores spaced on the first cores die to correspond to all or a first subset of the landing slots on the uncore die, each of the cores having an inter-die interface positioned to be communicatively coupled to a corresponding inter-die interface within a landing slot on the uncore die when the first cores die is vertically coupled on top of the uncore die.

Claims

1. A method comprising:

mounting an uncore die on a package, the uncore die comprising a plurality of exposed landing slots, each landing slot including an inter-die interface usable to connect vertically to a cores die, the uncore die including a plurality of uncore components usable by cores within the cores die including a memory controller component, a level 3 (L3) cache, a system memory or system memory interface, and a core interconnect fabric or bus;

vertically coupling a first cores die comprising a first plurality of cores on top of the uncore die, the cores spaced on the first cores die to correspond to all or a first subset of the landing slots on the uncore die, each of the cores having an inter-die interface positioned to be communicatively coupled to a corresponding inter-die interface within a landing slot on the uncore die when the first cores die is vertically coupled on top of the uncore die, wherein the communicative coupling between the inter-die interface of a core and the inter-die interface of its corresponding landing slot communicatively couples the core to the uncore components of the uncore die; and

vertically coupling a second cores die comprising a second plurality of cores on top of the uncore die, the cores of the second plurality spaced on the second cores die to correspond to a second subset of the landing slots on the uncore die different from the first subset, each of the cores on the second cores die having an inter-die interface positioned to be communicatively coupled to a corresponding inter-die interface within a landing slot on the uncore die when the second cores die is vertically coupled on top of the uncore die with the first cores die, wherein the communicative coupling between the inter-die interface of a core and the inter-die interface of its corresponding landing slot communicatively couples the core to the uncore components of the uncore die.

2. The method as in claim 1 wherein the second plurality of cores comprise lower power and lower performance cores relative to the first plurality of cores which comprise higher power and higher performance cores relative to the second plurality of cores.

3. The method as in claim 1 wherein the uncore die further comprises power management logic to manage power usage by cores on the core die and a fully integrated voltage regulator (FIVR) to manage voltage levels on the cores die and the uncore die.

4. The method as in claim 1 wherein the uncore die further comprises a plurality of Through-Silicon-Vias (TSVs) coupled to the inter-die interfaces exposed on the landing slots, the TSVs providing communicative coupling through the uncore die to the uncore components and/or to one or more lines on the package.

5. The method as in claim 1 wherein the inter-die interfaces of the uncore die and the first cores die comprise micro-bumps usable for aligning the inter-die interfaces of the uncore die and the first cores die.

6. The method as in claim 1 wherein the uncore die is fabricated using a first silicon fabrication process and the first cores die is fabricated using a second silicon fabrication process different from the first silicon fabrication process.

7. The method as in claim 6 wherein the second silicon fabrication process is a newer silicon fabrication process than the first silicon fabrication process.

8. A method comprising:

mounting an uncore die on a package, the uncore die comprising a plurality of exposed landing slots, each landing slot including an inter-die interface usable to connect vertically to a cores die, the uncore die including a plurality of uncore components usable by cores within the cores die including a memory controller component, a level 3 (L3) cache, a system memory or system memory interface, and a core interconnect fabric or bus;

vertically coupling a first cores die comprising a first plurality of cores on top of the uncore die, the cores spaced on the first cores die to correspond to all or a first subset of the landing slots on the uncore die, each of the cores having an inter-die interface positioned to be communicatively coupled to a corresponding inter-die interface within a landing slot on the uncore die when the first cores die is vertically coupled on top of the uncore die, wherein the communicative coupling between the inter-die interface of a core and the inter-die interface of its corresponding landing slot communicatively couples the core to the uncore components of the uncore die; and

vertically coupling a graphics subsystem die comprising one or more graphics cores on top of the uncore die, each of the graphics cores spaced on the graphics subsystem die to correspond to a second subset of the landing slots on the uncore die different from the first subset, each of the graphics cores on the graphics subsystem die having an inter-die interface positioned to be communicatively coupled to a corresponding inter-die interface within a landing slot on the uncore die when the graphics subsystem die is vertically coupled on top of the uncore die with the first cores die, wherein the communicative coupling between the inter-die interface of a graphics core and the inter-die interface of its corresponding landing slot communicatively couples the graphics core to the uncore components of the uncore die.

9. The method as in claim 8 wherein the uncore die is fabricated using a first silicon fabrication process and the graphics subsystem die is fabricated using a second silicon fabrication process different from the first silicon fabrication process.

10. The method as in claim 8 wherein the uncore die further comprises power management logic to manage power usage by cores on the core die and a fully integrated voltage regulator (FIVR) to manage voltage levels on the cores die and the uncore die.

11. The method as in claim 8 wherein the uncore die further comprises a plurality of Through-Silicon-Vias (TSVs) coupled to the inter-die interfaces exposed on the landing slots, the TSVs providing communicative coupling through the uncore die to the uncore components and/or to one or more lines on the package.

12. The method as in claim 8 wherein the inter-die interfaces of the uncore die and the first cores die comprise micro-bumps usable for aligning the inter-die interfaces of the uncore die and the first cores die.

13. The method as in claim 8 wherein the uncore die is fabricated using a first silicon fabrication process and the first cores die is fabricated using a second silicon fabrication process different from the first silicon fabrication process.

14. The method as in claim 13 wherein the second silicon fabrication process is a newer silicon fabrication process than the first silicon fabrication process.