Methods of forming circuit-protection devices

• US 10,431,577 B2
• Filed: 02/09/2018
• Issued: 10/01/2019
• Est. Priority Date: 12/29/2017
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Smith, Michael A., Marr, Kenneth W.
• Primary Examiner(s): Nguyen, Thanh T
• Application Number:
  US15/892,625
• Publication Number:
  US 20190206856A1
• Time in Patent Office: 599 Days
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/22 Safety or protection circuits preventing unauthorised or accidental access to memory cells
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: H01L 21/28035 the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities H01L21/28105 takes precedence
• CPC Class Codes: H01L 21/28158 Making the insulator
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H01L 27/1266 the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

Methods of forming a circuit-protection device include forming a dielectric having a first thickness and a second thickness greater than the first thickness over a semiconductor, forming a conductor over the dielectric, and patterning the conductor to retain a portion of the conductor over a portion of the dielectric having the second thickness, and to retain substantially no portion of the conductor over a portion of the dielectric having the first thickness, wherein the retained portion of the conductor defines a control gate of a field-effect transistor of the circuit-protection device.

Claims

1. A method of forming a circuit-protection device, comprising:

forming a dielectric having a first thickness and having a second thickness, greater than the first thickness, over a semiconductor;

forming the dielectric further having a third thickness greater than the second thickness, over the semiconductor;

forming a conductor over the dielectric;

patterning the conductor to retain a first portion of the conductor over a portion of the dielectric having the second thickness, and to retain substantially no portion of the conductor over a portion of the dielectric having the first thickness; and

patterning the conductor to further retain a second portion of the conductor over a portion of the dielectric having the third thickness;

wherein the retained first portion of the conductor defines a control gate of a first field-effect transistor of the circuit-protection device; and

wherein the retained second portion of the conductor defines a control gate of a second field-effect transistor of the circuit-protection device connected in series with the first field-effect transistor.

2. A method of forming a circuit-protection device, comprising:

forming a first dielectric over a first portion of a semiconductor;

forming a second dielectric over the first portion of the semiconductor, over a second portion of the semiconductor, and over a third portion of the semiconductor;

removing a portion of the second dielectric over the third portion of the semiconductor;

forming a third dielectric over the first portion of the semiconductor, over the second portion of the semiconductor, and over the third portion of the semiconductor;

forming a conductor over the third dielectric; and

patterning the conductor to retain a first portion of the conductor over the first portion of the semiconductor and a second portion of the conductor over the second portion of the semiconductor.

3. The method of claim 2, further comprising removing a portion of the first dielectric prior to forming the second dielectric.

4. The method of claim 2, wherein forming the second dielectric comprises forming the second dielectric to comprise the first dielectric, and wherein forming the third dielectric comprises forming the third dielectric to comprise the second dielectric.

5. The method of claim 2, further comprising removing a portion of the third dielectric over the third portion of the semiconductor.

6. The method of claim 5, wherein removing the portion of the third dielectric over the third portion of the semiconductor comprises removing an entire portion of the third dielectric over the third portion of the semiconductor.

7. The method of claim 2, further comprising patterning the conductor to retain substantially no portion of the conductor over the third portion of the semiconductor.