Semiconductor devices with multi-gate structure and method of manufacturing the same

• US 10,431,585 B2
• Filed: 12/04/2017
• Issued: 10/01/2019
• Est. Priority Date: 12/16/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Yang, Jung-Gil, Bae, Geum-Jong, Bae, Dong-Il, Song, Seung-Min, Park, Woo-Seok
• Primary Examiner(s): Ngo, Ngan V
• Application Number:
  US15/830,981
• Publication Number:
  US 20180175035A1
• Time in Patent Office: 666 Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0646 PN junctions
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0669 Nanowires or nanotubes carbon nanotubes as material of solid-state device active part H10K85/211
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/413 Nanosized electrodes, e.g. nanowire electrodes comprising one or a plurality of nanowires nanosized carbon materials, e.g. carbon nanotubes, per se C01B32/15; transparent electrodes comprising carbon nano-tubes H10K30/821, nanotechnology per se B82B
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66742 : Thin film unipolar transistors
• CPC Class Codes: H01L 29/66772 : Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/775 : with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7853 : the body having a non-rectangular crossection
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H01L 2924/13086 : Junctionless Nanowire Transistor [JNT]

Abstract

A semiconductor device includes a first transistor in a first region and a second transistor in a second region. The first transistor includes: a first nanowire, a first gate electrode, a first gate dielectric layer, a first source/drain region, and an inner-insulating spacer. The first nanowire has a first channel region. The first gate electrode surrounds the first nanowire. The first gate dielectric layer is between the first nanowire and the first gate electrode. The first source/drain region is connected to an edge of the first nanowire. The inner-insulating spacer is between the first gate dielectric layer and the first source/drain region. The second transistor includes a second nanowire, a second gate electrode, a second gate dielectric layer, and a second source/drain region. The second nanowire has a second channel region. The second gate electrode surrounds the second nanowire. The second gate dielectric layer is between the second nanowire and the second gate electrode. The second source/drain region is connected to an edge of the second nanowire.

Claims

1. A semiconductor device, comprising:

a first transistor in a first region of a substrate and a second transistor in a second region of the substrate,

wherein the first transistor comprises;

a first nanowire having a first channel region;

a first gate electrode surrounding the first nanowire;

a first gate dielectric layer between the first nanowire and the first gate electrode;

a first source/drain region connected to an edge of the first nanowire; and

an inner-insulating spacer between the first gate dielectric layer and the first source/drain region,

the second transistor comprises;

a second nanowire having a second channel region;

a second gate electrode surrounding the second nanowire;

a second gate dielectric layer between the second nanowire and the second gate electrode; and

a second source/drain region connected to an edge of the second nanowire,

the second gate dielectric layer extends between the second gate electrode and the second source/drain region and is in contact with the second source/drain region, and

the first source/drain region is not in contact with the first gate dielectric layer.

2. The semiconductor device of claim 1, wherein the first gate dielectric layer extends between the first gate electrode and the inner-insulating spacer.

3. The semiconductor device of claim 1, wherein the inner-insulating spacer comprises a first material having a first dielectric constant, and the first gate dielectric layer and second gate dielectric layer comprise a second material having a second dielectric constant greater than the first dielectric constant.

4. The semiconductor device of claim 1, further comprising:

a first external insulating spacer surrounding sides of the first gate electrode,

wherein the first external insulating spacer and the inner-insulating spacer overlap and are located over the substrate at different levels from each other in a direction perpendicular to the substrate.

5. The semiconductor device of claim 4,

wherein the first external insulating spacer and the inner-insulating spacer comprise different materials from each other.

6. The semiconductor device of claim 1, further comprising:

a second external insulating spacer surrounding sides of the second gate electrode on the second nanowire,

wherein the second external insulating spacer and the second gate electrode overlap and are is located over the substrate at different levels from each other in a direction perpendicular to the substrate.

7. The semiconductor device of claim 1,

wherein the second source/drain region comprises at least one protrusion portion, and the at least one protrusion portion contacts the second gate dielectric layer.

8. The semiconductor device of claim 1, further comprising a buffer layer extending along a main surface extension direction of the substrate between the substrate and the first gate electrode and between the substrate and the second gate electrode, wherein the buffer layer comprises a material having a lattice constant greater than a lattice constant of the substrate.

9. The semiconductor device of claim 1, further comprising:

a first channel separation region between the substrate and the first gate electrode and extending along a main surface extension direction of the substrate, wherein the first channel separation region includes a conductive type dopant different from that of the first source/drain region; and

a second channel separation region between the substrate and the second gate electrode and extending along the main surface extension direction of the substrate, wherein the second channel separation region includes a conductive type dopant different from that of the second source/drain region.

10. The semiconductor device of claim 1, wherein the first transistor is an n-type metal-oxide-semiconductor (NMOS) transistor, and the second transistor is a p-type metal-oxide-semiconductor (PMOS) transistor.

11. A semiconductor device, comprising:

a first transistor in a first region of a substrate and a second transistor in a second region of the substrate,

wherein the first transistor comprises;

a plurality of first nanowires having a plurality of first channel regions;

a first gate electrode surrounding the plurality of first nanowires;

a first gate dielectric layer between the plurality of first nanowires and the first gate electrode;

a first source/drain region connected to an edge of the plurality of first nanowires; and

an inner-insulating spacer between the first gate dielectric layer and the first source/drain region,

the second transistor comprises;

a plurality of second nanowires having a plurality of second channel regions;

a second gate electrode surrounding the plurality of second nanowires;

a second gate dielectric layer between the plurality of second nanowires and the second gate electrode; and

a second source/drain region connected to an edge of the plurality of second nanowires,

the second gate dielectric layer extends between the second gate electrode and the second source/drain region and is in contact with the second source/drain region, and

a distance between the first gate electrode and the first source/drain region in a first direction that is an extension direction of the plurality of first nanowires is larger than a distance between the second gate electrode and the second source/drain region in the first direction.

12. The semiconductor device of claim 11, wherein the first gate dielectric layer extends between the first gate electrode and the inner-insulating spacer, and

the first source/drain region is not in contact with the first gate dielectric layer.

13. The semiconductor device of claim 11, wherein the first gate dielectric layer and the inner-insulating spacer are disposed between the first gate electrode and the first source/drain region, and

the second gate dielectric layer is disposed between the second gate electrode and the second source/drain region.

14. The semiconductor device of claim 11, further comprising:

a first external insulating spacer surrounding sides of the first gate electrode on the plurality of first nanowires; and

a second external insulating spacer surrounding sides of the second gate electrode on the plurality of second nanowires,

wherein the first external insulating spacer and the inner-insulating spacer overlap and are located at different levels from each other over the substrate in a direction perpendicular to the substrate, and

the second external insulating spacer and the second gate electrode overlap and are located at different levels from each other over the substrate in a direction perpendicular to the substrate.

15. A semiconductor device, comprising:

a substrate with a first region and a second region;

a first transistor in the first region of the substrate and comprising a first nanowire, a first gate dielectric layer, a first source region, a first drain region, an inner-insulating spacer, and a first gate electrode surrounding the first nanowire, and

a second transistor in the second region of the substrate comprising a second nanowire, a second gate dielectric layer, a second source region, a second drain region, a second gate electrode surrounding the second nanowire,

wherein the first gate dielectric layer is provided between the first nanowire and the first gate electrode, and between the inner-insulating spacer and the first gate electrode,

wherein the inner-insulating spacer maintains a space between the first gate dielectric layer and the first source region and the first drain region,

wherein the second gate dielectric layer is provided between the second nanowire and the second gate electrode, between the second source region and the second gate electrode, and between the second drain region and the second gate electrode,

wherein the first source region and first drain region are not in contact with the first gate dielectric layer, and

wherein the second source region and second drain region are in contact with the second gate dielectric layer.

16. The semiconductor device of claim 15, further comprising:

a first external insulating spacer laterally surrounding the first gate electrode on a side of the first nanowire opposite from the inner-insulating spacer and from the substrate,

wherein a second external insulating spacer surrounds the second gate electrode laterally on a side of the second nanowire opposite from the substrate.

17. The semiconductor device of claim 15,

wherein the first nanowire channels electrons between the first source region and the first drain region, and the second nanowire channels holes between the second source region and the second drain region.

18. The semiconductor device of claim 15,

wherein the first transistor comprises at least one third nanowire that channels electrons between the first source region and the first drain region and that is surrounded by the first gate electrode,

wherein the first gate dielectric layer is provided between each of the first nanowire and the at least one third nanowires and the first gate electrode,

wherein the inner-insulating spacer is provided between each of the first nanowire and third nanowires in a direction perpendicular to the substrate,

wherein the second transistor comprises at least one fourth nanowire that channels holes between the second source region and the second drain region and that is surrounded by the second gate electrode, and

wherein the second gate dielectric layer is provided between each of the second nanowire and the at least one fourth nanowires and the second gate electrode.