Nanosheet transistor with robust source/drain isolation from substrate

• US 10,431,651 B1
• Filed: 04/30/2018
• Issued: 10/01/2019
• Est. Priority Date: 04/30/2018
• Status: Active Grant

• Current Assignee: Rapidus Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Chao, Robin Hsin Kuo, Cheng, Kangguo, Chi, Cheng, Xie, Ruilong, Zhang, John H.
• Primary Examiner(s): Amer, Mounir S
• Application Number:
  US15/967,524
• Time in Patent Office: 519 Days
• Field of Search: None
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0669 Nanowires or nanotubes carbon nanotubes as material of solid-state device active part H10K85/211
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A substrate structure for a nanosheet transistor includes a plurality of nanosheet layers and a plurality of recesses between the nanosheet layers. The substrate structure includes at least one trench through portions of the nanosheet layers, the sacrificial layers, and the substrate. The substrate structure includes a u-shaped portion formed at a bottom portion of the at least one trench. The u-shaped portion includes a bottom cavity. The substrate structure further includes a first liner disposed upon the u-shaped portion of the at least one trench, and a second liner disposed on the first liner. The substrate structure further includes a third liner disposed within the at least one trench to fill the bottom cavity of the u-shaped portion to form a bottom inner spacer within the bottom cavity.

Claims

1. A method of fabricating a nanosheet transistor comprising:

receiving a substrate structure having a plurality of nanosheet layers and a plurality of sacrificial layers stacked upon a substrate;

forming at least one trench through portions of the nanosheet layers, the sacrificial layers, and the substrate;

depositing a first liner within the at least one trench;

depositing a second liner on the first liner;

selectively removing portions of the second liner to form a u-shaped portion at a bottom portion of the at least one trench, the u-shaped portion including a bottom cavity;

selectively removing portions of the first liner to a level of a top portion of the u-shaped portion at the bottom portion of the at least one trench;

selectively laterally etching edges of each of the sacrificial layers to create recesses within the sacrificial layers; and

depositing a third liner within the at least one trench to fill the recesses and the bottom cavity of the u-shaped portion.

2. The method of claim 1, further comprising:

etching the third liner to form side inner spacers adjacent to the sacrificial layers and a bottom inner spacer within the bottom cavity.

3. The method of claim 2, further comprising:

depositing a source/drain epitaxy upon the bottom inner spacer.

4. The method of claim 3, further comprising:

removing portions of the sacrificial layers; and

depositing a gate material within voids left by removal of the sacrificial layers.

5. The method of claim 4, wherein the gate material includes a high-K metallic gate (HKMG) material.

6. The method of claim 3, further comprising:

forming a dummy gate upon a top nanosheet layer of the plurality of nanosheet layers.

7. The method of claim 6, further comprising:

removing portions of the dummy gate; and

depositing a gate material within a void left by removal of the dummy gate.

8. The method of claim 7, further comprising:

forming an insulative cap upon the gate material;

depositing an interlayer dielectric layer upon the insulative cap; and

forming at least one contact within the interlayer dielectric layer and the insulative cap in contact with the source/drain epitaxy.

9. The method of claim 1, further comprising:

depositing, prior to selectively removing the second liner, an organic planarizing layer (OPL) within the at least one trench; and

removing the OPL prior to the selective lateral etching of edges of each of the sacrificial layers.

10. The method of claim 1, wherein the first liner is formed of an oxide material.

11. The method of claim 1, wherein the second liner is formed of a nitride material.

12. The method of claim 1, wherein the third liner is formed of a nitride material.

13. The method of claim 1, wherein the first liner is thinner than the second liner.

14. The method of claim 1, wherein the nanosheet layers are formed of a silicon (Si) material.

15. The method of claim 1, wherein the sacrificial layers are formed of a silicon-germanium (SiGe) material.