Fabrication of a vertical fin field effect transistor with a reduced contact resistance

• US 10,431,659 B2
• Filed: 06/01/2017
• Issued: 10/01/2019
• Est. Priority Date: 06/24/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Miao, Xin, Xu, Wenyu, Zhang, Chen
• Primary Examiner(s): Yushina, Galina G
• Application Number:
  US15/611,388
• Publication Number:
  US 20170373162A1
• Time in Patent Office: 852 Days
• CPC Class Codes: H01L 2029/7858 having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1041 with a non-uniform doping structure in the channel region surface
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method of forming a vertical fin field effect transistor (vertical finFET) with an increased surface area between a source/drain contact and a doped region, including forming a doped region on a substrate, forming one or more interfacial features on the doped region, and forming a source/drain contact on at least a portion of the doped region, wherein the one or more interfacial features increases the surface area of the interface between the source/drain contact and the doped region compared to a flat source/drain contact-doped region interface.

Claims

1. A vertical fin field effect transistor (vertical finFET) with an increased surface area between a bottom source/drain contact and a doped region, comprising:

the doped region on a substrate;

one or more vertical fins on the doped region; and

the bottom source/drain contact on at least a portion of the same doped region as the one or more vertical fins, wherein the doped region has a plurality of interfacial features that increases the surface area of an interface between the bottom source/drain contact and the doped region compared to a flat bottom source/drain contact-doped region interface, wherein each of the plurality of interfacial features has the same width and lengths as each of the one or more vertical fins.

2. The vertical finFET of claim 1, wherein the doped region and the bottom source/drain contact are electrically coupled together.

3. The vertical finFET of claim 1, further comprising a gate structure formed on the one or more vertical fins on the same doped region as the bottom source/drain contact.

4. The vertical finFET of claim 1, further comprising a top source/drain on at least one of the one or more vertical fins, and a top source/drain contact formed on the top source/drain.

5. The vertical finFET of claim 1, wherein the plurality of interfacial features that increases the surface area of the interface are a plurality of doped extensions that extend into the bottom source/drain contact.

6. The vertical finFET of claim 1, wherein the plurality of interfacial features that increases the surface area of the interface are a plurality of recesses that allows the bottom source/drain contact to extend into the doped region.

7. A vertical fin field effect transistor (vertical finFET) with an increased surface area between a bottom source/drain contact and a doped region, comprising:

the doped region on a substrate;

one or more vertical fins on the doped region; and

the bottom source/drain contact on at least a portion of the same doped region as the one or more vertical fins and electrically coupled to the same doped region, wherein the doped region has a plurality of doped extensions that extend into the bottom source/drain contact that increases the surface area of an interface between the bottom source/drain contact and the doped region compared to a flat bottom source/drain contact-doped region interface, wherein each of the plurality of doped extensions has the same width and length as each of the one or more vertical fins.

8. The vertical finFET of claim 7, wherein each of the plurality of doped extensions has a height in the range of about 10 nm to about 40 nm.

9. The vertical finFET of claim 8, wherein the doped region and each of the plurality of doped extensions include n-type dopants.

10. The vertical finFET of claim 8, wherein the doped region and each of the plurality of doped extensions include p-type dopants.

11. The vertical finFET of claim 8, wherein the bottom source/drain contact is tungsten, copper, titanium, aluminum, or combinations thereof.

12. The vertical finFET of claim 11, further comprising a gate structure formed on one or more vertical fins on the same doped region as the bottom source/drain contact, wherein each of the one or more vertical fins has a width in a range of about 6 nm to about 20 nm.

13. The vertical finFET of claim 12, further comprising a top source/drain on the one or more vertical fins, and a top source/drain contact formed on the top source/drain.

14. A vertical fin field effect transistor (vertical finFET) with an increased surface area between a bottom source/drain contact and a doped region, comprising:

the doped region on a substrate;

one or more vertical fins on the doped region; and

the bottom source/drain contact on at least a portion of the same doped region as the one or more vertical fins and electrically coupled to the same doped region, wherein

the doped region has a plurality of recesses that extend into the surface of the doped region that increases the surface area of an interface between the bottom source/drain contact and the doped region compared to a flat bottom source/drain contact-doped region interface, wherein

each of the plurality of recesses has the same width and length as each of the one or more vertical fins and a depth greater than the width of the one or more vertical fin.

15. The vertical finFET of claim 14, wherein each of the plurality of recesses do not extend all the way through the doped region.

16. The vertical finFET of claim 14, wherein each of the plurality of recesses has a depth in the range of about 10 nm to about 40 nm.

17. The vertical finFET of claim 16, wherein each of the plurality of recesses has a width in the range of about 6 nm to about 20 nm, and a length in the range of about 100 nm to about 1000 nm.

18. The vertical finFET of claim 17, wherein the bottom source/drain contact is tungsten, copper, titanium, aluminum, or combinations thereof, and the bottom source/drain contact fills the recesses.

19. The vertical finFET of claim 18, further comprising a gate structure formed on one or more vertical fins on the same doped region as the bottom source/drain contact.

20. The vertical finFET of claim 19, further comprising a top spacer layer on the gate structure, and a top source/drain on the one or more vertical fins, and a top source/drain contact formed on the top source/drain.