Method of making a semiconductor switch device

• US 10,431,666 B2
• Filed: 03/26/2018
• Issued: 10/01/2019
• Est. Priority Date: 05/17/2017
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Al-Sa'di, Mahmoud Shehab Mohammad, Magnee, Petrus Hubertus Cornelis
• Primary Examiner(s): Garber, Charles D
• Assistant Examiner(s): Sabur, Alia
• Application Number:
  US15/935,306
• Publication Number:
  US 20180337250A1
• Time in Patent Office: 554 Days
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A semiconductor switch device and a method of making the same. The method includes providing a semiconductor substrate having a major surface and a first semiconductor region having a first conductivity type. The method further includes implanting ions into the first semiconductor region through an opening in a mask positioned over the first semiconductor region, thereby to form a well region located in the first semiconductor region, the well region having a second conductivity type different to the first conductivity type. The method also includes depositing and patterning a gate electrode material on a gate dielectric to form a gate electrode located directly above the well region. The method further includes performing ion implantation to form a source region located in the well region on a first side of the gate, and to form a drain region located outside the well region on a second side of the gate.

Claims

1. A method of making a semiconductor switch device, the method comprising:

providing a semiconductor substrate having;

a major surface; and

a first semiconductor region having a first conductivity type located adjacent the major surface;

depositing a gate dielectric on the major surface of the substrate;

implanting ions into the first semiconductor region through an opening in a mask positioned over the first semiconductor region, thereby to form a well region located in the first semiconductor region, the well region having a second conductivity type different to the first conductivity type;

depositing and patterning a gate electrode material on the gate dielectric to form a gate electrode located directly above the well region; and

performing ion implantation to;

form a source region having said first conductivity type located in the well region on a first side of the gate electrode, and

form a drain region having said first conductivity type located outside the well region on a second side of the gate electrode;

wherein a lateral dimension of the opening in the mask is substantially equal to L_source+L_g+MTL;

wherein L_source is a length of the source region measured from an edge of the gate electrode on the first side of the gate electrode;

wherein L_g is a gate length of the semiconductor switch device; and

wherein MTL is a mask tolerance of the opening, and wherein MTL≤

400 nm.

2. The method of claim 1,

wherein the gate electrode is located toward one side of the well region when viewed from above the major surface of the semiconductor substrate.

3. The method of claim 2,

wherein the drain region is located adjacent the side of the well region toward which the gate electrode is located.

4. The method of claim 1,

wherein an edge of the gate electrode located on said second side of the gate electrode is located directly above an edge of the well region.

5. The method of claim 1,

wherein the mask tolerance MTL is in the range 0-200 nm.

6. The method of claim 5,

wherein the gate length L_g is less than 1 μ

m.

7. The method of claim 1, further comprising

implanting ions into the first semiconductor region through the opening in the mask positioned over the first semiconductor region,

thereby to adjust a threshold voltage of the semiconductor switch device.

8. The method of claim 1, further comprising

implanting ions into the first semiconductor region through the opening in the mask positioned over the first semiconductor region,

thereby to inhibit punch-through in the semiconductor switch device.

9. The method of claim 1, comprising

forming spacers on opposed sidewalls of the gate electrode prior to said performing ion implantation to form the source region and the drain region.

10. The method of claim 1,

wherein the first conductivity type is n-type and wherein the second conductivity type is p-type.

11. The method of claim 1,

wherein the first semiconductor region comprises a doped epitaxial layer.

12. The method of claim 1,

wherein the switch device is a Radio Frequency (RF) switch device.