Semiconductor device

• US 10,431,677 B2
• Filed: 02/08/2016
• Issued: 10/01/2019
• Est. Priority Date: 03/27/2015
• Status: Active Grant

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Nakano, Yuki
• Primary Examiner(s): Campbell, Shaun M
• Application Number:
  US15/561,800
• Publication Number:
  US 20180114856A1
• Time in Patent Office: 1,331 Days
• Field of Search: None
• CPC Class Codes: H01L 29/06 characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/12 characterised by the materials of which they are formed
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/4925 with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with only a vertical doping structure or vertical doping variation H01L29/4916
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

The semiconductor device of the present invention includes a semiconductor layer which includes an active portion and a gate finger portion, an MIS transistor which is formed at the active portion and includes a gate trench as well as a source region, a channel region and a drain region sequentially along a side surface of the gate trench, a plurality of first gate finger trenches arranged by an extended portion of the gate trench at the gate finger portion, a gate electrode embedded each in the gate trench and the first gate finger trench, a second conductive-type first bottom-portion impurity region formed at least at a bottom portion of the first gate finger trench, a gate finger which crosses the plurality of first gate finger trenches and is electrically connected to the gate electrode, and a second conductive-type electric field relaxation region which is formed more deeply than the bottom portion of the first gate finger trench between the mutually adjacent first gate finger trenches.

Claims

1. A semiconductor device comprising:

a semiconductor layer of SiC which includes an active portion;

a plurality of MIS transistors which are formed at the active portion, the active portion partitioned into the plurality of MIS transistors by a plurality of gate trenches, and each of the MIS transistors having a first conductive-type source region, a second conductive-type channel region, and a first conductive-type drain region sequentially along a side surface of the gate trench;

a plurality of first gate finger trenches which are arranged by extended portions of the gate trenches at a gate finger portion;

a gate electrode embedded in each of the gate trenches and the first gate finger trenches via a gate insulating film;

a second conductive-type first bottom-portion impurity region which is formed at least at a bottom portion of the first gate finger trenches;

a gate finger which is electrically connected to the first gate finger trenches and the gate electrode;

a source electrode formed over the semiconductor layer;

a conductive film between the source electrode and the semiconductor layer, having a second insulating film between the conductive film and the semiconductor layer, the conductive film being present only on the second insulating film, the source electrode being in direct contact with a second conductive-type channel contact region in the semiconductor layer, and the conductive film being between two adjacent gate trenches;

and;

a second conductive-type electric field relaxation region which is formed more deeply than a bottom portion of the first gate finger trench.

2. The semiconductor device according to claim 1 which additionally includes a plurality of second gate finger trenches, each of which is formed between an adjacent pair of the first gate finger trenches and being integral with the gate trench,

wherein the electric field relaxation region includes a second bottom-portion impurity region formed at least at a bottom portion of the second gate finger trenches.

3. The semiconductor device according to claim 2, wherein the second gate finger trenches extend along the first gate finger trenches.

4. The semiconductor device according to claim 2, wherein the second gate finger trenches extend in a direction which intersects with the first gate finger trenches.

5. The semiconductor device according to claim 1, wherein a region between an adjacent pair of the first gate finger trenches includes a flat region in which a surface of the semiconductor layer continues from a first of the first gate finger trenches to a second of the first gate finger trenches,

the region additionally includes in the flat region a second conductive-type surface-portion impurity region which is formed more shallowly than the bottom portion of the first gate finger trenches, and

the electric field relaxation region includes a region formed so as to continue to the surface-portion impurity region.

6. The semiconductor device according to claim 1, wherein a region between an adjacent pair of the first gate finger trenches includes a flat region in which the surface of the semiconductor layer continues from a first of the first gate finger trenches to a second of the first gate finger trenches,

the region additionally includes in the flat region a second conductive-type surface-portion impurity region which is formed more shallowly than the bottom portion of the first gate finger trenches, and

the electric field relaxation region includes a region which is formed below the surface-portion impurity region, with a clearance kept.

7. The semiconductor device according to claim 1, wherein each of the MIS transistors additionally includes a second conductive-type region which continues to the channel region and is formed more deeply than the electric field relaxation region.

12. The semiconductor device according to claim 1, wherein

the gate electrode is provided with an overlap portion which overlaps with the surface of the semiconductor layer at an upper edge of a trench in which the gate electrode is embedded, and

the gate insulating film includes an overhung portion which protrudes inside the trench at the upper edge.

13. The semiconductor device according to claim 12, wherein the upper edge includes an inclined surface which allows the surface of the semiconductor layer to continue to an inner surface of the trench.

14. The semiconductor device according to claim 12, wherein

the upper edge includes a circular surface which allows the surface of the semiconductor layer to continue to the inner surface of the trench.

15. The semiconductor device according to claim 12, wherein the gate insulating film on the bottom surface of the trench is thicker than the gate insulating film on the side surface of the trench.

16. The semiconductor device according to claim 12, wherein the gate insulating film additionally includes on the surface of the semiconductor layer a portion which is thicker than the gate insulating film on the side surface of the trench.

17. The semiconductor device according to claim 12, wherein a lower edge of the trench includes a circular surface which allows the side surface of the trench to continue to the bottom surface thereof.

18. The semiconductor device according to claim 1, wherein the semiconductor layer is composed of a wide band gap semiconductor.

19. The semiconductor device according to claim 1, wherein avalanche breakdown preferentially occurs at the active portion rather than the gate finger portion.

8. A semiconductor device comprising:

a semiconductor layer which includes an active portion and a gate finger portion;

a plurality of MIS transistors which are formed at the active portion, the active portion partitioned into the plurality of MIS transistors by a plurality of gate trenches formed at a predetermined pitch P₁, each of the MIS transistors having a first conductive-type source region, a second conductive-type channel region, and a first conductive-type drain region sequentially along a side surface of the gate trench;

a plurality of gate finger trenches which are formed in the gate finger portion at a pitch P₂ narrower than the pitch P₁ of the gate trenches and being integral with the gate trenches;

a gate electrode embedded each in the gate trench and the gate finger trench via a gate insulating film;

a second conductive-type bottom-portion impurity region which is formed at least at a bottom portion of the gate finger trench; and

a gate finger which crosses the plurality of gate finger trenches and is electrically connected to the gate electrode.

9. The semiconductor device according to claim 8, wherein the gate trenches are formed in a lattice shape, and

the gate finger trenches include a plurality of first gate finger trenches which are arranged by an extended portion of the gate trenches and arrayed at a lattice pitch of the gate trenches and second gate finger trenches formed between adjacent pairs of the first gate finger trenches.

10. The semiconductor device according to claim 8, wherein each of the MIS transistors additionally includes a second conductive-type region which continues to the channel region and is formed more deeply than the bottom portion impurity region.

11. The semiconductor device according to claim 8, wherein the bottom portion impurity region is electrically connected to the channel region.