Preparation methods for semiconductor layer and TFT, TFT and array substrate comprising semiconductor layer

• US 10,431,692 B2
• Filed: 05/20/2016
• Issued: 10/01/2019
• Est. Priority Date: 03/07/2016
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: Meng, Hu
• Primary Examiner(s): Ojeh, Nduka E
• Application Number:
  US15/533,128
• Publication Number:
  US 20180108783A1
• Time in Patent Office: 1,229 Days
• Field of Search: 257 40, 257E5104, 438149
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/4958 with a multiple layer structure
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78633 with a light shield
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10K 10/464 Lateral top-gate IGFETs comprising only a single gate
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs
• CPC Class Codes: H10K 85/221 Carbon nanotubes

Abstract

Embodiments of the present disclosure provide preparation methods for a semiconductor layer and a TFT, a TFT and an array substrate. The preparation method for a semiconductor layer includes forming a silicon dioxide film on a substrate; forming sidewalls at two ends of the semiconductor layer to be formed by patterning process; performing amination treatment on the sidewalls so that an aminosiloxane monolayer self-assembly is formed on the surface of the sidewalls; carboxylating a carbon nanotube solution and making the carboxylated carbon nanotube solution on the surface of the substrate with the sidewalls formed to form a carbon nanotube film; removing portions of the carbon nanotube film other than the portion between the sidewalls to form a semiconductor layer.

Claims

1. A preparation method for a transistor, comprising:

forming a silicon dioxide insulating layer as sidewalls at two opposing ends of a semiconductor layer to be formed on a flexible substrate;

subjecting two opposing surfaces of the sidewalls to amination treatment using aminopropyltriethoxy silane (APTES) solution so that an aminosiloxane monolayer self-assembly is formed on the two opposing surfaces of the sidewalls;

carboxylating a carbon nanotube solution and making the carboxylated carbon nanotube solution on a surface of the flexible substrate and between the two opposing surfaces formed with the aminosiloxane monolayer self-assembly to form a carbon nanotube film between the two opposing surfaces;

removing portions of the carbon nanotube film above a top surface of the sidewalls to form the semiconductor layer no higher than the top of the sidewalls;

forming a gate insulating film on the semiconductor layer;

forming via holes in the gate insulating layer;

forming a metal film by vapor deposition or sputtering process; and

forming a source and a drain at the via holes by patterning process such that the source and the drain are in contact with the semiconductor layer.

2. The preparation method according to claim 1, wherein subjecting the sidewalls to amination treatment comprises:

dip coating or spraying an aminopropylsilane solution on the substrate with the sidewalls formed.

3. The preparation method according to claim 1, wherein carboxylating a carbon nanotube solution comprises:

mixing an oxidizing agent with the carbon nanotube solution to carboxylate the carbon nanotube solution.

4. The preparation method according to claim 1, wherein

a gate, the source and the drain are formed by one patterning process.

5. The preparation method according to claim 1, wherein forming the gate insulating layer comprises:

forming a gate insulating film on the substrate with the semiconductor layer formed, forming a via hole penetrating the gate insulating film and the semiconductor layer by patterning process to form the gate insulating layer,

wherein the via hole is immediately close to the sidewalls.