Trench semiconductor device having multiple active trench depths and method

• US 10,431,699 B2
• Filed: 03/06/2015
• Issued: 10/01/2019
• Est. Priority Date: 03/06/2015
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Quddus, Mohammed Tanvir, Mudholkar, Mihir, Thomason, Michael
• Primary Examiner(s): Parker, Kenneth
• Assistant Examiner(s): Lin, John
• Application Number:
  US14/640,242
• Publication Number:
  US 20160260845A1
• Time in Patent Office: 1,670 Days
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/66143 Schottky diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

In one embodiment, a trench Schottky rectifier includes a termination trench and active trenches provided in a semiconductor layer. A first active trench is configured to be at a shallower depth than the termination trench to provide a trench depth difference. A second active trench is configured to be at a depth similar to the termination trench. The selected trench depth difference in combination with one or more of the other second active trench depth, the dopant concentration of the semiconductor layer, the thickness of the semiconductor layer, first active trench width to termination trench width, and/or dopant profile of the semiconductor layer provide a semiconductor device having improved performance characteristics.

Claims

1. A semiconductor device comprising:

a region of semiconductor material having a first conductivity type and a major surface;

a first active trench extending from a first portion of the major surface into the region of semiconductor material to a first depth, wherein the first active trench has a first width;

a second active trench extending from a second portion of the major surface into the region of semiconductor material to a second depth, wherein the second active trench has a second width, and wherein the second depth is greater than the first depth;

a third trench extending from a fourth portion of the major surface into the region of semiconductor material to a third depth, wherein the third trench is configured as a termination trench, and wherein the third trench is disposed at an edge of the semiconductor device such that the third trench is an outermost trench for the semiconductor device, and wherein the third trench is laterally interposed between the edge and the first and second active trenches, and wherein the third depth is greater than the first depth, and wherein the third trench has a third width that is greater than the first width and the second width;

a first conductive material within the first active trench and separated from the region of semiconductor material by a first dielectric region;

a second conductive material within the second active trench and separated from the region of semiconductor material by a second dielectric region;

a third conductive material adjoining a third portion of the major surface, wherein the third conductive material is configured to provide a Schottky barrier;

a conductive spacer disposed along a sidewall of the third trench and separated from the region of semiconductor material by a third dielectric region that adjoins sidewall and lower surfaces of the third trench; and

a dielectric layer different than the third dielectric region disposed adjacent the conductive spacer within the third trench such that the conductive spacer is laterally interposed between the dielectric layer and the third dielectric region, wherein;

the third depth is greater than the first depth in a range greater than zero to approximately 3.0 microns;

the third depth and the second depth are substantially equal;

the third conductive material physically contacts the conductive spacer; and

the first active trench is interposed between the second active trench and the third trench.

2. The semiconductor device of claim 1, wherein:

the first active trench is one of a plurality of first active trenches each having the first depth;

the second active trench is one of a plurality of second active trenches each having the second depth;

one of the plurality of first active trenches is interposed between one of the plurality of second active trenches and the third trench in cross-sectional view;

another one of the plurality of first active trenches is interposed between a pair of second active trenches in the cross-sectional view; and

the third depth is greater than the first depth in a range greater than zero to approximately 2.0 microns.

3. The semiconductor device of claim 1, wherein:

the second width is different than the first width;

the semiconductor device further comprises;

a third active trench extending from a fifth portion of the major surface to the first depth; and

a fourth conductive material within the third active trench and separated from the region of semiconductor material by a third dielectric region; and

the second active trench is interposed between the first active trench and the third active trench in a cross-sectional view such that the second active trench is closer to the edge of the semiconductor device than the third active trench.

4. The semiconductor device of claim 1, wherein the semiconductor device has a first width to third width ratio in a range from approximately 0.005 to approximately 0.125.

5. The semiconductor device of claim 1, wherein the semiconductor device comprises a first width to third width ratio less than or equal to approximately 0.03.

6. The semiconductor device of claim 1, wherein:

the region of semiconductor material comprises a semiconductor layer adjoining a semiconductor substrate;

the semiconductor layer defines the major surface; and

the semiconductor layer has a first dopant concentration and the semiconductor substrate has a second dopant concentration greater than the first dopant concentration.

7. The semiconductor device of claim 6, wherein:

the semiconductor layer has a thickness from approximately 1.0 micron to approximately 15 microns; and

the first dopant concentration is in a range from approximately 5.0×

10¹³ atoms/cm³ and approximately 5.0×

10¹⁷ atoms/cm³.

8. The semiconductor device of claim 6, wherein the semiconductor layer has a non-uniform dopant profile.

9. The semiconductor device of claim 1, wherein the first dielectric region and the second dielectric regions have different thicknesses.

10. The semiconductor device of claim 1, wherein the first dielectric region has a thickness in a range from approximately 0.05 microns to approximately 0.6 microns.

11. The semiconductor device of claim 1 further comprising a doped layer adjoining the third portion of the major surface adjacent to the third conductive material, wherein the doped layer has a fourth depth less than the first depth.

12. The semiconductor device of claim 1, wherein the first width and the second width are approximately the same.

13. A semiconductor device comprising:

a region of semiconductor material comprising a semiconductor layer adjoining a semiconductor substrate, the semiconductor layer defining a major surface, wherein the semiconductor layer has a first dopant concentration and the semiconductor substrate has a second dopant concentration greater than the first dopant concentration;

a termination trench extending from a first portion of the major surface into the region of semiconductor material, wherein the termination trench extends to a first depth, and wherein the termination trench has a first width, and wherein the termination trench is disposed at an edge portion of the semiconductor device such that the termination trench is an outermost trench for the semiconductor device;

first active trenches extending from second portions of the major surface into the region of semiconductor material to a second depth, wherein the first active trenches have a second width less than the first width, and wherein the first depth is greater than the second depth to define a trench depth difference;

second active trenches extending from third portions of the major surface into the region of semiconductor material to a third depth greater than the second depth, wherein the second active trenches have a third width;

a first conductive material within the first active trenches and the second active trenches and each separated from the region of semiconductor material by a first dielectric region; and

a second conductive material adjoining a fourth portion of the major surface, wherein the second conductive material is configured to provide a Schottky barrier, wherein;

the first active trenches and the second active trenches are provided in an alternating configuration such that at least one of the first active trenches is interposed between a pair of second active trenches in a cross-sectional view.

14. The semiconductor device of claim 13, wherein:

the trench depth difference is greater than zero but less than approximately 3.0 microns;

another first active trench disposed as a closest active trench to the termination trench and is further interposed between the termination trench and one of the second active trenches in the cross-sectional view;

the semiconductor layer has a thickness from approximately 1.0 micron to approximately 15 microns; and

the first dopant concentration is in a range from approximately 5.0×

10¹³ atoms/cm³ and approximately 5.0×

10¹⁷ atoms/cm³.

15. The semiconductor device of claim 13, wherein:

the semiconductor device comprises a second width to first width ratio less than or equal to approximately 0.03;

the second width and the third width are different; and

the first depth, the second depth, and the third depth are different.

16. A Schottky semiconductor device comprising:

a region of semiconductor material comprising a semiconductor layer adjoining a semiconductor substrate, the semiconductor layer defining a major surface, wherein the semiconductor layer has a first dopant concentration and the semiconductor substrate has a second dopant concentration greater than the first dopant concentration;

a termination trench extending from a first portion of the major surface into the region of semiconductor material, wherein the termination trench extends to a first depth, and wherein the termination trench has a first width, and wherein the termination trench is disposed at an edge of the region of semiconductor material such that the termination trench is an outermost trench for the Schottky semiconductor device;

a conductive spacer disposed along a sidewall of the termination trench and separated from the region of semiconductor material by a first dielectric region that adjoins sidewall and lower surfaces of the termination trench;

a dielectric layer disposed adjacent a sidewall surface of the conductive spacer within the termination trench such that the conductive spacer is laterally interposed between the dielectric layer and the first dielectric region;

a first active trench extending from a second portion of the major surface into the region of semiconductor material to a second depth, wherein the first active trench has a second width less than the first width, wherein the second depth is less than the first depth;

a second active trench extending from a third portion of the major surface into the region of semiconductor material to a third depth greater than the second depth, wherein the second active trench has a third width less than the first width;

a third active extending from a fourth portion of the major surface into the region of semiconductor material to the third depth, wherein the third active trench has the third width, and wherein the first active trench is laterally interposed between the second active trench and the third active trench in a cross-sectional view; and

a conductive material adjoining a fourth portion of the major surface, wherein the conductive material is configured to provide a Schottky barrier.

17. The Schottky semiconductor device of claim 16, wherein:

the first depth is greater than the second depth to provide a trench depth difference; and

the trench depth difference is greater than zero and less than approximately 3.0 microns.

18. The Schottky semiconductor device of claim 16, wherein:

the Schottky semiconductor device has a first width to third width ratio less than or equal to approximately 0.03; and

the first depth, the second depth, and the third depth are different.

19. The Schottky semiconductor device of claim 16, wherein:

the Schottky semiconductor device comprises a first width to third width ratio less than or equal to approximately 0.03; and

the first depth and the third depth are substantially equal.

20. The Schottky semiconductor device of claim 16 further comprising:

a second dielectric structure disposed within the first active trench; and

a third dielectric structure disposed within the second active trench.

21. The Schottky semiconductor device of claim 20, wherein:

the third dielectric structure has a first thickness along sidewalls of the second active trench;

the second dielectric structure has a second thickness along sidewalls of the first active trench; and

the first thickness is greater than the second thickness.

22. A semiconductor device comprising:

a region of semiconductor material having a first conductivity type and a major surface;

a first active trench extending from a first portion of the major surface into the region of semiconductor material to a first depth, wherein the first active trench has a first width;

a second active trench extending from a second portion of the major surface into the region of semiconductor material to a second depth, wherein the second active trench has a second width, and wherein the second depth is greater than the first depth;

a third trench extending from a fourth portion of the major surface into the region of semiconductor material to a third depth, wherein the third trench is configured as a termination trench, and wherein the third trench is disposed at an edge of the semiconductor device such that the third trench is an outermost trench for the semiconductor device, and wherein the third trench is laterally interposed between the edge and the first and second active trenches, and wherein the third depth is greater than the first depth, and wherein the third trench has a third width that is greater than the first width and the second width;

a first conductive material within the first active trench and separated from the region of semiconductor material by a first dielectric region;

a second conductive material within the second active trench and separated from the region of semiconductor material by a second dielectric region; and

a third conductive material adjoining a third portion of the major surface, wherein the third conductive material is configured to provide a Schottky barrier, wherein;

the first active trench is one of a plurality of first active trenches each having the first depth;

the second active trench is one of a plurality of second active trenches each having the second depth;

one of the plurality of first active trenches is interposed between one of the plurality of second active trenches and the third trench in cross-sectional view;

another one of the plurality of first active trenches is interposed between a pair of second active trenches in the cross-sectional view; and

the third depth is greater than the first depth in a range greater than zero to approximately 3.0 microns.

23. The semiconductor device of claim 22, wherein the third depth and the second depth are different.

24. The semiconductor device of claim 22, wherein the semiconductor device comprises a first width to third width ratio less than or equal to approximately 0.03.