Unbalanced multiplexer and scan flip-flops applying the same

• US 10,436,836 B2
• Filed: 10/24/2016
• Issued: 10/08/2019
• Est. Priority Date: 03/28/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Min-Su
• Primary Examiner(s): Knapp, Justin R
• Application Number:
  US15/332,305
• Publication Number:
  US 20170276729A1
• Time in Patent Office: 1,079 Days
• Field of Search: None
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: G01R 31/31725 Timing aspects, e.g. clock distribution, skew, propagation delay for tester hardware G01R31/31937
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318541 Scan latches or cell details
• CPC Class Codes: G01R 31/31858 Delay testing

Abstract

An unbalanced multiplexer and a scan flip-flop including the unbalanced multiplexer, wherein the unbalanced multiplexer includes a first transmission circuit transmitting a first input signal to an output terminal according to a logic state of a selection signal; and a second transmission circuit transmitting a second input signal to the output terminal according to the logic state of the selection signal. A delay characteristic of a first transmission path from a first input terminal to the output terminal along which the first input signal of the first transmission circuit is transmitted, and a delay characteristic of a second transmission path from a second input terminal to the output terminal along which the second input signal of the second transmission circuit is transmitted, are set differently.

Claims

1. An unbalanced multiplexer comprising:

a first transmission circuit comprising a first pull-up circuit connected between a source voltage terminal and an output terminal, and a first pull-down circuit connected between the output terminal and a ground voltage terminal, the first transmission circuit configured to apply a selection signal and a first input signal to the first pull-up circuit and to apply the first input signal and an inverted version of the selection signal to the first pull-down circuit, and to transmit the first input signal to the output terminal according to a logic state of the selection signal; and

a second transmission circuit comprising a second pull-up circuit connected between the source voltage terminal and the output terminal, and a second pull-down circuit connected between the output terminal and the ground voltage terminal, the second transmission circuit configured to apply the selection signal and a second input signal to the second pull-down circuit and to apply the second input signal and the inverted version of the selection signal to the second pull-up circuit, and to transmit the second input signal to the output terminal according to the logic state of the selection signal,

wherein a delay characteristic of a first transmission path from a first input terminal to the output terminal along which the first input signal of the first transmission circuit is transmitted, and a delay characteristic of a second transmission path from a second input terminal to the output terminal along which the second input signal of the second transmission circuit is transmitted, are set to be different.

2. The unbalanced multiplexer of claim 1, wherein a data signal is applied to the first input terminal as the first input signal, a scan input signal is applied to the second input terminal as the second input signal, the selection signal is a scan enable signal, and the second transmission path is configured to have a delay time that is greater than a delay time of the first transmission path.

3. The unbalanced multiplexer of claim 1, wherein the first pull-up circuit comprises first group p-type metal-oxide-semiconductor (PMOS) transistors connected between the source voltage terminal and the output terminal in a cascode arrangement, the first pull-down circuit comprises second group n-type metal-oxide-semiconductor (NMOS) transistors connected between the output terminal and the ground voltage terminal in a cascode arrangement, the second pull-up circuit comprises third group PMOS transistors connected between the source voltage terminal and the output terminal in a cascode arrangement, and the second pull-down circuit comprises fourth group NMOS transistors connected between the output terminal and the ground voltage terminal in a cascode arrangement,

wherein the selection signal is a scan enable signal that is applied to a gate of one of the first group PMOS transistors, the inverted version of the selection signal is an inverted version of the scan enable signal that is applied to a gate of one of the second group NMOS transistors, and the first input signal is a data signal that is applied to a gate of each of the first group PMOS transistors other than the one of the first group PMOS transistors and each of the second group NMOS transistors other than the one of the second group NMOS transistors,

wherein the inverted version of the scan enable signal is applied to a gate of one of the third group PMOS transistors, the scan enable signal is applied to a gate of one of the fourth group NMOS transistors, and the second input signal is a scan input signal that is applied to a gate of each of the third group PMOS transistors other than the one of the third group PMOS transistors and each of the fourth group NMOS transistors other than the one of the fourth group NMOS transistors, and

wherein the second pull-up circuit or the second pull-down circuit is configured to have a delay time when the scan input signal is transmitted to the output terminal through the second pull-up circuit or the second pull-down circuit that is greater than a delay time when the data signal is transmitted to the output terminal through the first pull-up circuit or the first pull-down circuit.

4. The unbalanced multiplexer of claim 3, wherein a number of transistors having gates to which the scan input signal is applied from among the third group PMOS transistors and the fourth group NMOS transistors is greater than a number of transistors having gates to which the data signal is applied from among the first group PMOS transistors and the second group NMOS transistors.

5. The unbalanced multiplexer of claim 4, wherein a number of the third group PMOS transistors having gates to which the scan input signal is applied is the same as a number of the fourth group NMOS transistors having gates to which the scan input signal is applied.

6. The unbalanced multiplexer of claim 4, wherein a number of the third group PMOS transistors having gates to which the scan input signal is applied and a number of the fourth group NMOS transistors having gates to which the scan input signal is applied are asymmetrically different from each other.

7. The unbalanced multiplexer of claim 4, wherein one of a number of the third group PMOS transistors having gates to which the scan input signal is applied and a number of the fourth group NMOS transistors having gates to which the scan input signal is applied is greater than the other.

8. The unbalanced multiplexer of claim 3, wherein a number of the first group PMOS transistors and a number of the third group PMOS transistors are the same, a number of the second group NMOS transistors and a number of the fourth group NMOS transistors are the same, and a length of a gate of at least one of the third group PMOS transistors or the fourth group NMOS transistors is greater than a length of a gate of each of the first group PMOS transistors and the second group NMOS transistors.

9. The unbalanced multiplexer of claim 3, wherein a number of the first group PMOS transistors and a number of the third group PMOS transistors are the same, a number of the second group NMOS transistors and a number of the fourth group NMOS transistors are the same, and at least one of the third group PMOS transistors or the fourth group NMOS transistors is configured to have a threshold voltage higher than a threshold voltage of each of the first group PMOS transistors and the second group NMOS transistors.

10. An unbalanced multiplexer comprising:

a first transmission circuit configured to transmit a first signal along a first transmission path from a first input terminal to an output terminal according to a logic state of a selection signal,

wherein the first transmission path comprises first group p-type metal-oxide-semiconductor (PMOS) transistors in a cascode arrangement connected to second group n-type metal-oxide-semiconductor (NMOS) transistors in a cascode arrangement; and

a second transmission circuit configured to transmit a second signal along a second transmission path from a second input terminal to the output terminal according to the logic state of the selection signal,

wherein the second transmission path comprises third group PMOS transistors in a cascode arrangement connected to fourth group NMOS transistors in a cascode arrangement,

wherein the first transmission path is configured to have a delay characteristic that is set to be different than a delay characteristic of the second transmission path,

wherein a number of transistors in the first group PMOS transistors, a number of transistors in the second group NMOS transistors, a number of transistors in the third group PMOS transistors and a number of transistors in the fourth group NMOS transistors are the same, and

a length of a gate of at least one of the transistors in the third group PMOS transistors and a length of a gate in at least one of the transistors in the fourth group NMOS transistors are greater than a length of each of the transistors in the first group PMOS transistors and in the second group NMOS transistors.

11. An unbalanced multiplexer of claim comprising:

a first transmission circuit configured to transmit a first signal along a first transmission path from a first input terminal to an output terminal according to a logic state of a selection signal,

wherein the first transmission path comprises first group p-type metal-oxide-semiconductor (PMOS) transistors in a cascode arrangement connected to second group n-type metal-oxide-semiconductor (NMOS) transistors in a cascode arrangement; and

a second transmission circuit configured to transmit a second signal along a second transmission path from a second input terminal to the output terminal according to the logic state of the selection signal,

wherein the second transmission path comprises third group PMOS transistors in a cascode arrangement connected to fourth group NMOS transistors in a cascode arrangement,

wherein the first transmission path is configured to have a delay characteristic that is set to be different than a delay characteristic of the second transmission path,

wherein a number of transistors in the first group PMOS transistors, a number of transistors in the second group NMOS transistors, a number of transistors in the third group PMOS transistors and a number of transistors in the fourth group NMOS transistors are the same, and

a threshold voltage of at least one of the transistors in the third group PMOS transistors and a threshold voltage of at least one of the transistors in the fourth group NMOS transistors are higher than a threshold voltage of each of the transistors in the first group PMOS transistors and in the second group NMOS transistors.