Integrated light-emitting pixel arrays based devices by bonding

• US 10,437,402 B1
• Filed: 03/27/2018
• Issued: 10/08/2019
• Est. Priority Date: 03/27/2018
• Status: Active Grant

• Current Assignee: Shaoher Pan
• Original Assignee: Shaoher Pan
• Inventors: Pan, Shaoher
• Primary Examiner(s): Feliciano, Eliseo Ramos
• Assistant Examiner(s): Singal, Ankush K
• Application Number:
  US15/937,735
• Publication Number:
  US 20190302917A1
• Time in Patent Office: 560 Days
• CPC Class Codes: G06F 2203/04102 Flexible digitiser, i.e. constructional details for allowing the whole digitising part of a device to be flexed or rolled like a sheet of paper
• CPC Class Codes: G06F 3/044 by capacitive means
• CPC Class Codes: H01L 23/5387 Flexible insulating substrates H01L23/5388 takes precedence
• CPC Class Codes: H01L 25/0753 the devices being arranged next to each other
• CPC Class Codes: H01L 25/167 comprising optoelectronic devices, e.g. LED, photodiodes
• CPC Class Codes: H01L 27/1218 with a particular composition or structure of the substrate
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1266 the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
• CPC Class Codes: H01L 29/78678 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 2933/0041 relating to wavelength conversion elements
• CPC Class Codes: H01L 2933/0058 relating to optical field-shaping elements
• CPC Class Codes: H01L 2933/0066 relating to arrangements for conducting electric current to or from the semiconductor body
• CPC Class Codes: H01L 2933/0083 Periodic patterns for optical field-shaping in or on the semiconductor body or semiconductor body package, e.g. photonic bandgap structures
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/06 within the light emitting region, e.g. quantum confinement structure or tunnel barrier
• CPC Class Codes: H01L 33/32 containing nitrogen
• CPC Class Codes: H01L 33/405 Reflective materials
• CPC Class Codes: H01L 33/44 characterised by the coatings, e.g. passivation layer or anti-reflective coating
• CPC Class Codes: H01L 33/502 : Wavelength conversion materials
• CPC Class Codes: H01L 33/504 : Elements with two or more wavelength conversion materials
• CPC Class Codes: H01L 33/507 : the elements being in intimate contact with parts other than the semiconductor body or integrated with parts other than the semiconductor body
• CPC Class Codes: H01L 33/58 : Optical field-shaping elements
• CPC Class Codes: H01L 33/62 : Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

Integrated active-matrix light emitting pixel arrays based displays and methods of fabricating the integrated displays are provided. An example method includes: forming multiple layers on a first substrate to form a light emitting structure, integrating the light emitting structure on the first substrate with a backplane device on a second substrate by connecting a first top layer of the light emitting structure with a second top layer of the backplane device, e.g., by using low temperature bonding, the backplane device including at least one backplane having pixel circuits, and after the integration, patterning the light emitting structure to form an array of light emitting elements each conductively coupled to respective pixel circuits to thereby form an array of active-matrix light emitting pixels. A pattern of different color phosphor or different size quantum dots materials can be deposited on the light emitting pixels to form an array of multi-color display pixels.

Claims

1. A method of fabricating an integrated device, the method comprising:

forming a plurality of layers on a first substrate to form a light emitting structure;

integrating the formed light emitting structure on the first substrate with a backplane device formed on a second substrate by connecting a first top layer of the light emitting structure with a second top layer of the backplane device, wherein the backplane device includes at least one backplane having a plurality of pixel circuits; and

after the integration, patterning the light emitting structure to form a plurality of separate light emitting elements each conductively coupled to respective pixel circuits of the plurality of pixel circuits to thereby form a plurality of active-matrix light emitting pixels, wherein each of the active-matrix light emitting pixels comprises at least one of the light emitting elements and at least one of the pixel circuits conductively coupled to the at least one of the light emitting elements.

2. The method of claim 1, wherein each of the pixel circuits comprises a non-volatile memory including at least one transistor conductively coupled to a corresponding drive electrode in the second top layer, and

wherein the non-volatile memory is conductively coupled to a corresponding light emitting element in a respective active-matrix light emitting pixel through the corresponding drive electrode.

3. The method of claim 2, wherein the at least one backplane comprises scanning drivers and data drivers, and

wherein each of the non-volatile memories is coupled to one of the scanning drivers through at least one word line and to one of the data drivers through at least one bit line.

4. The method of claim 1, wherein the plurality of layers includes a contact electrode layer as the first top layer, and each of the pixel circuits is coupled to a respective drive electrode in the second top layer, and

wherein each of the pixel circuits is conductively coupled to the light emitting structure through the respective drive electrode and the contact electrode layer.

5. The method of claim 4, wherein the contact electrode layer comprises a doped semiconductor layer, and

wherein the contact electrode layer is patterned to form individual Ohmic contacts of the separate light emitting elements.

6. The method of claim 1, wherein integrating the formed light emitting structure on the first substrate with the backplane device formed on the second substrate comprises:

using low temperature bonding to bond the first top layer of the light emitting structure on the second top layer of the backplane device through an intermediate conductive layer.

7. The method of claim 6, comprising:

simultaneously patterning the light emitting structure and the intermediate conductive layer, wherein each of the light emitting elements is self-aligned with a respective patterned intermediate conductive layer.

8. The method of claim 6, wherein the intermediate conductive layer comprises one or more metallic films including:

an iridium-tin-oxide (ITO) film with a titanium (Ti) film,

a copper (Cu) film with a Tantalum (Ta) film,

an aluminum (Al) film with a Tin (Sn) film, or

a gold (Au) or silver (Ag) film with at least one adhesive film including chromium (Cr), Platinum (Pt), Palladium (Pd), or Titanium (Ti).

9. The method of claim 1, wherein the first substrate comprises a first semiconductor wafer and the second substrate comprises a second semiconductor wafer, and

wherein integrating the formed light emitting structure on the first substrate with the backplane device formed on the second substrate comprises:

aligning the first semiconductor wafer with the second semiconductor wafer face-to-face at a wafer-to-wafer level of accuracy.

10. The method of claim 1, wherein integrating the formed light emitting structure on the first substrate with the backplane device formed on the second substrate comprises:

aligning the formed light emitting structure on the first substrate with a first region of the backplane device on the second substrate; and

bonding the light emitting structure with the first region of the backplane device.

11. The method of claim 10, further comprising integrating another light emitting structure on another first substrate with the backplane device on the second substrate by

aligning the another light emitting structure on the another first substrate with a second region of the backplane device;

and

bonding the another light emitting structure with the second region of the backplane device, the second region being adjacent to the particular region.

12. The method of claim 10, further comprising:

scanning, by using a laser, an area with a particular shape on the light emitting structure such that the light emitting structure in the area is separated from the first substrate and remains bonded on the backplane device; and

removing the first substrate together with other non-scanned areas on the light emitting structure from the first region of the backplane device.

13. The method of claim 12, further comprising:

aligning another light emitting structure on another first substrate with a second region of the backplane device on the second substrate;

bonding the another light emitting structure with the second region of the backplane device;

scanning, by using the laser, a second area with the particular shape on the another light emitting structure such that the another light emitting structure in the second area is separated from the another first substrate and remains bonded on the backplane device; and

removing the another first substrate together with other non-scanned areas on the another light emitting structure from the second region of the backplane device,

wherein the another light emitting structure on the another first substrate is aligned with the second region of the backplane device on the second substrate, such that the another light emitting structure in the second area is adjacent to the light emitting structure in the first area on the backplane device.

14. The method of claim 1, wherein each of the pixel circuits is coupled to a respective drive electrode in the second top layer, and

wherein the method further comprises:

before the patterning, aligning a protective mask with the respective drive electrodes in the second top layer, such that dielectric materials between the respective drive electrodes in the second top layer are selectively etched away after the patterning.

15. The method of claim 1, further comprising:

before the patterning, removing the first substrate from the light emitting structure to expose the light emitting structure.

16. The method of claim 15, wherein the light emitting structure comprises one or more quantum well layers as an active medium between the first top layer as a first contact electrode and a second contact electrode,

wherein the light emitting structure comprises a buffer layer between the second contact electrode and the first substrate, and

wherein the method further comprises:

polishing the light emitting structure to remove the buffer layer to expose the second contact electrode.

17. The method of claim 16, wherein the method further comprises:

thinning the second contact electrode by polishing to remove a portion of the second contact electrode.

18. The method of claim 15, wherein removing the first substrate from the light emitting structure comprises:

using laser lift-off or laser scribing.

19. The method of claim 1, further comprising:

filling an isolation material in gaps between adjacent light emitting elements of the plurality of light emitting elements.

20. The method of claim 19, wherein the isolation material comprises an opaque dielectric material.

21. The method of claim 19, wherein the light emitting structure comprises one or more quantum well layers as an active medium between the first top layer as a first contact electrode and a second contact electrode, and

wherein the method further comprises:

polishing the light emitting elements filled with the isolation material to expose the second contact electrodes in the light emitting elements and form a flat surface across the second contact electrodes of the light emitting elements.

22. The method of claim 21, further comprising:

depositing a transparent conductive layer on the flat surface to connect the second contact electrodes of the light emitting elements to form a common electrode for the light emitting elements.

23. The method of claim 1, further comprising:

forming a conductive grid array package on a bottom of the second substrate opposite to the second top layer, the conducive grid array package being conductively coupled to the at least one backplane.

24. The method of claim 23, wherein the conductive grid array package comprises a ball grid array (BGA) package.

25. The method of claim 1, wherein the formed light-emitting structure comprises one or more quantum well layers including Group III-V compounds and is configured to be activated to emit light with a primary color, and each of the light emitting elements is configured to emit light with the primary color.

26. The method of claim 25, wherein each of the light emitting elements comprises a light emitting diode (LED).

27. The method of claim 1, wherein each of the light-emitting elements is operable to emit light with a first color,

wherein the method further comprises:

forming a plurality of active-matrix multi-color display pixels using the plurality of active-matrix light-emitting pixels, each display pixel including at least a particular pixel element to emit light with a second color, the second color being different from the first color.

28. The method of claim 27, wherein each display pixel comprises at least three pixel elements operable to emit light with at least three different colors including red, blue, and green.

29. The method of claim 27, wherein forming the plurality of active-matrix multi-color display pixels comprises:

patterning with photoresist to select particular light-emitting elements of the plurality of light-emitting elements;

depositing phosphor films or a quantum-dot films on the selected light-emitting elements, wherein the selected light-emitting elements with the deposited phosphor films or the quantum-dot films are operable to emit the second color when the phosphor films or the quantum-dot films are excited by light from the selected light-emitting elements; and

removing the photoresist to form the particular pixel elements of the display pixels.

30. The method of claim 27, wherein each of the light-emitting elements is operable to emit ultraviolet (UV) or deep UV light with a wavelength between 100 nm and 450 nm.

31. The method of claim 30, wherein forming the plurality of active-matrix multi-color display pixels comprises:

forming at least three different color phosphor films or different size quantum-dot films on at least three light-emitting elements in each of the display pixels, wherein the display pixel is operable to emit at least blue, red, and green colors when the phosphor films or quantum-dot films are excited by the UV or deep UV light from the at least three light-emitting elements.

32. The method of claim 27, wherein each of the light-emitting elements is operable to emit light with a blue color.

33. The method of claim 32, wherein forming the plurality of active-matrix multi-color display pixels comprises:

forming at least two different color phosphor films or different size quantum-dot films on at least two light-emitting elements in each of the display pixels, wherein the display pixel is operable to emit at least red and green colors when the phosphor films or quantum-dot films are excited by the blue light from the at least two light-emitting elements.

34. The method of claim 33, wherein forming the plurality of active-matrix multi-color display pixels comprises:

forming a transparent layer on a third light-emitting element in the display pixel,

wherein the display pixel is operable to emit a blue color from the third light-emitting element.

35. The method of claim 27, wherein each display pixel comprises a first pixel element and a second pixel element that have respective first light conversion efficiency and second light conversion efficiency when excited by the light-emitting elements,

wherein patterning the light emitting structure to form a plurality of separate light emitting elements comprises:

patterning the light emitting structure to form a plurality of first light emitting elements each having a first area, the first light emitting elements being for the first pixel elements; and

patterning the light emitting structure to form a plurality of second light emitting elements each having a second area, the second light emitting elements being for the second pixel elements, and

wherein an area ratio between the first area and the second area is based on a ratio between the first light conversion efficiency and the second light conversion efficiency.

36. The method of claim 27, further comprising:

forming an isolation spacer between adjacent pixel elements of the display pixels, wherein the isolation spacer comprises an opaque dielectric material.

37. The method of claim 27, further comprising:

forming a transparent protective layer on top of the plurality of active-matrix multi-color di splay pixels.

38. The method of claim 37, wherein the formed transparent protective layer comprises a transparent touch-sensitive protective layer, and

wherein the transparent touch-sensitive protective layer is configured to form, together with a common electrode of the light emitting elements, a capacitive touch screen position sensor.

39. The method of claim 37, further comprising:

forming a polarizer film between the protective layer and the display pixels.

40. The method of claim 1, wherein the first substrate comprises one of a single crystal silicon semiconductor substrate and a sapphire substrate, and

wherein the plurality of layers comprises epitaxial semiconductor layers grown on the first substrate.

41. The method of claim 1, wherein the at least one backplane comprises a complementary metal-oxide-semiconductor (CMOS) backplane.

42. The method of claim 1, wherein the backplane device comprises an array of backplanes formed on the second substrate and separable from each other.

43. The method of claim 1, wherein the second substrate comprises a flexible film on a rigid substrate.

44. The method of claim 43, further comprising:

removing the rigid substrate such that the integrated device fabricated on the flexible film becomes flexible.

45. The method of claim 1, wherein the at least one backplane comprises a low temperature polysilicon (LTPS) thin-film transistors (TFT) array control backplane.

46. The method of claim 1, wherein each of the active-matrix light emitting pixels is drivable by a current source.

47. A method of fabricating an integrated active-matrix LED pixel array based display by bonding, the method comprising:

epitaxially growing a plurality of semiconductor layers on a first substrate to form a light emitting diode (LED) structure, the semiconductor layers including one or more quantum well layers having Group III-V compounds between a first doped semiconductor layer as a first contact electrode and a second doped semiconductor layer as a second contact electrode;

forming an intermediate metal layer on a top layer of a backplane device formed on a second substrate, the backplane device including at least one backplane having a plurality of non-volatile memories, each of the non-volatile memories being conductively coupled to a respective drive electrode in the top layer of the backplane device;

integrating the LED structure on the first substrate with the backplane device on the second substrate by low temperature bonding including bonding the first doped semiconductor layer of the LED structure with the top layer of the backplane device via the intermediate metal layer, wherein each of the non-volatile memories is conductively coupled to the LED structure via the respective drive electrode, the intermediate metal layer and the first contact electrode;

after the integration, patterning the LED structure together with the intermediate metal layer and the bonded top layer of the backplane device to form an array of LEDs each conductively coupled to respective non-volatile memories of the plurality of non-volatile memories to thereby form an array of active-matrix LED pixels, wherein each of the active-matrix LED pixels comprises at least one of the LEDs and at least one of the non-volatile memories conductively coupled to the at least one of the LEDs;

forming an array of active-matrix multi-color display pixels by selectively depositing different color phosphor materials or different size quantum dots materials on surfaces of the LEDs in each of the active-matrix LED pixels, each display pixel including at least three pixel elements operable to emit light with three colors including red, blue, and green when excited by the LEDs; and

forming a transparent protective layer on the array of active-matrix multi-color display pixels.

48. The method of claim 47, further comprising:

forming first isolation spacers between adjacent LEDs of the array of LEDs, the first isolation spacers including an opaque dielectric material;

polishing the array of LEDs with the first isolation spacers to expose the second doped semiconductor layers of the LEDs and to form a flat surface across the array of LEDs;

depositing a transparent conductive layer on the flat surface to form a common electrode for the array of active-matrix LED pixels;

forming second isolation spacers between adjacent pixel elements of the display pixels and on the transparent conductive layer, the second isolation spacers comprising the opaque dielectric material; and

forming a polarizer film between the transparent protective layer and the array of active-matrix multi-color display pixels,

wherein the different color phosphor materials or quantum dots materials are selectively patterned on the transparent conductive layer, and

wherein the transparent protective layer is touch-sensitive and configured to form, together with the common electrode, a capacitive touch screen position sensor.

49. The method of claim 47, wherein the at least one backplane comprises a complementary metal-oxide-semiconductor (CMOS) backplane, and the second substrate comprises a silicon semiconductor wafer,

wherein the first substrate comprises one of a silicon semiconductor wafer and a sapphire wafer,

wherein the method further comprising:

before the integration, aligning the first substrate with the second substrate at a wafer-to-wafer level of accuracy;

after the integration, removing the first substrate by laser lift-off to expose the LED structure and polishing the LED structure to expose the second doped semiconductor layer;

before the patterning, aligning a protective mask with the respective drive electrodes in the top layer of the backplane device, such that dielectric materials between the respective drive electrodes in the top layer are selectively etched away after the patterning; and

forming a ball grid array (BGA) package on a bottom layer of the second substrate opposite to the top layer and conductively coupled to the backplane device.

50. The method of claim 47, wherein the at least one backplane comprises a low temperature polysilicon (LTPS) active-matrix (AM) thin-film transistors (TFT) array control backplane, and the second substrate comprises a flexible film on a carrier substrate,

wherein the first substrate comprises one of a silicon semiconductor wafer and a sapphire wafer,

wherein integrating the formed LED structure on the first substrate with the TFT backplane device formed on the second substrate comprises:

aligning the formed LED structure on the first substrate with a first region of the TFT backplane device on the second substrate;

bonding the LED structure with the first region of the TFT backplane device;

scanning, by using a laser, a rectangular area on the LED structure such that the LED structure in the rectangular area is separated from the first substrate and remains bonded on the TFT backplane device; and

removing the first substrate together with other non-scanned areas on the LED structure from the first region of the TFT backplane device.

51. The method of claim 50, further comprising:

aligning another LED structure on another first substrate with a second region of the TFT backplane device on the second substrate;

bonding the another LED structure on the second region of the TFT backplane device;

scanning, by using the laser, a rectangular area on the another LED structure such that the another LED structure in the rectangular area is separated from the another first substrate and remains bonded on the TFT backplane device; and

removing the another first substrate together with other non-scanned areas on the another LED structure from the second region of the TFT backplane device,

wherein the another LED structure on the another first substrate is aligned with the second region of the TFT backplane device on the second substrate, such that the another LED structure in the second area is adjacent to the LED structure in the first area on the TFT backplane device.

52. The method of claim 47, wherein each of the display pixels includes first, second, and third pixel elements having respective first, second, and third light conversion efficiencies to emit a blue color, a green color, and a red color when excited by the LEDs,

wherein patterning the LED structure to form an array of LEDs comprises:

patterning the LED structure to form a plurality of first LEDs each having a first area, the first LEDs being for the first pixel elements;

patterning the LED structure to form a plurality of second LEDs each having a second area, the second LEDs being for the second pixel elements; and

patterning the LED structure to form a plurality of third LEDs each having a third area, the third LEDs being for the third pixel elements;

wherein an area ratio between the first area, the second area and the third area is based on a ratio between the first light conversion efficiency, the second light conversion efficiency, and the third light conversion efficiency.