Unified addressing and hierarchical heterogeneous storage and memory

• US 10,437,479 B2
• Filed: 12/04/2014
• Issued: 10/08/2019
• Est. Priority Date: 08/19/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Haghighi, Siamack, Brennan, Robert
• Primary Examiner(s): Thai, Tuan V
• Application Number:
  US14/561,204
• Publication Number:
  US 20160054933A1
• Time in Patent Office: 1,769 Days
• Field of Search: 711100, 711103, 711154, 711200
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 2212/205 Hybrid memory, e.g. using both volatile and non-volatile memory
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0649 Lifecycle management
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

According to one general aspect, an apparatus may include a processor, a heterogeneous memory system, and a memory interconnect. The processor may be configured to perform a data access on data stored in a memory system. The heterogeneous memory system may include a plurality of types of storage mediums. Each type of storage medium may be based upon a respective memory technology and may be associated with one or more performance characteristics. The heterogeneous memory system may include both volatile and non-volatile storage mediums. The memory interconnect may be configured to route the data access from the processor to at least one of the storage mediums based, at least in part, upon the one or more performance characteristic associated with the respective memory technologies of the storage media.

Claims

1. An apparatus comprising:

a processor configured to perform a data access on data stored in a memory system;

a heterogeneous memory system comprising a plurality of storage devices, wherein the plurality of storage devices comprise a plurality of types of storage devices, wherein each type of storage device is based upon a respective memory technology and wherein each respective memory technology is associated with one or more technology-based, physical performance characteristics, and wherein the heterogeneous memory system comprises at least one volatile storage device; and

a memory interconnect configured to;

locally route the data access from the processor to at least one of the plurality of storage devices based, at least in part, upon the one or more performance characteristics associated with the respective memory technologies of the plurality of storage media devices, and

communicate with each of the plurality of storage devices via a native protocol employed by the respective storage device.

2. The apparatus of claim 1, wherein the processor is configured to employ a unified access protocol regardless of the type of storage device employed to store the data.

3. The apparatus of claim 2, wherein the memory interconnect is configured to translate the data access from the unified access protocol employed by the processor to a storage device specific protocol employed by a storage device employed to store the data.

4. The apparatus of claim 1, wherein the plurality of storage devices includes a volatile system memory storage device and a non-volatile secondary storage device.

5. The apparatus of claim 4, wherein the volatile system memory storage device comprises a local, primary storage device for the processor.

6. The apparatus of claim 1, wherein the plurality of types of storage devices are based upon two or more different memory technologies.

7. The apparatus of claim 1, wherein the processor is configured to indicate, via the data access, a data category associated with the data stored in a memory system;

and

wherein the memory interconnect is configured to preferentially route the data to one of the plurality of types of storage devices based upon the data category.

8. The apparatus of claim 7, wherein the data category associated with the data is set during a compilation of a software program that, when executed by the processor, accesses the data.

9. The apparatus of claim 1, wherein the memory interconnect is configured to organize at least a portion of the plurality of storage devices into a hierarchy of storage device tiers based, at least in part upon, the one or more performance characteristics associated with each type of storage device.

10. The apparatus of claim 9, wherein the memory interconnect is configured to organize the hierarchy of storage device tiers into a layered caching memory system.

11. The apparatus of claim 9, wherein the memory interconnect is configured to dynamically re-organize the hierarchy of storage device tiers when the apparatus experiences a triggering event.

12. The apparatus of claim 1, wherein the memory interconnect comprises an integrated circuit that includes a memory controller circuit, at least one co-processor, a processor interface, and a plurality of storage device interfaces.

13. The apparatus of claim 1, wherein the processor and memory interconnect are integrated in a single circuit to form a system-on-a-chip.

14. The apparatus of claim 1, wherein the processor comprises the memory interconnect as part of the processor'"'"'s memory management unit.

15. The apparatus of claim 1, wherein the memory interconnect comprises

a memory controller configured to dynamically make a determination as to how to route the data access, and

at least one co-processor configured to support the memory controller in making the determination,

wherein the memory controller and at least one co-processor are integrated into a single circuit.

16. The apparatus of claim 15, wherein the at least one co-processor includes a direct memory access circuit.

17. The apparatus of claim 1, wherein the memory interconnect routes the data access via a non-frame-based, non-packet-based protocol.

18. The apparatus of claim 1, wherein the memory interconnect is configured to:

receive a data access in a unified, storage medium technology independent format, and

locally route the data access in a native, storage medium technology dependent format.

19. The apparatus of claim 1, wherein the memory interconnect comprises:

a plurality of memory interfaces configured to communicate with the heterogeneous memory system; and

a processing-side interface configured to communicate with the processor.

20. The apparatus of claim 1, wherein the memory interconnect is configured to operate, at least in part, as both a memory controller hub and an input/output controller hub.

21. A method comprising:

receiving, from a processor, a data access for a heterogeneous memory system,

wherein the heterogeneous memory system comprises a plurality of types of storage devices, wherein each type of storage device is based upon a respective memory technology and is associated with one or more performance characteristic;

determining, by a memory interconnect, a target storage device of the heterogeneous memory system for the data access based, at least in part, upon at least one performance characteristic associated with the target storage device; and

locally routing, by the memory interconnect, the data access, at least partially, between the processor and the target storage device, wherein the memory interconnect transmits the data access to the target storage device formatted via a protocol native to the target storage device.

22. The method of claim 21, wherein receiving the data access from the processor comprises:

receiving a data accesses for a first group of one or more storage devices via a first access protocol, and

receiving a data accesses for a second group of one or more storage devices via a second access protocol.

23. The method of claim 21, further comprising organizing at least a portion of the plurality of types of storage devices into a hierarchy of storage device tiers based, at least in part upon, the one or more performance characteristic associated with each type of storage device.

24. The method of claim 23, wherein organizing includes organizing the hierarchy of storage device tiers into a layered caching memory system,

wherein organizing the hierarchy of storage device tiers into a layered caching memory system includes monitoring the data accesses made to each storage device within the layered caching memory system, and

wherein determining includes determining which, if any, storage devices, include a piece of data associated with the data access.

25. The method of claim 23, wherein organizing includes organizing the hierarchy of storage device tiers into a layered caching memory system,

further including mirroring a piece of data within a non-volatile layer of the layered caching memory system, if the highest layer of the layered caching memory system that includes the piece of data includes a volatile storage device.

26. An apparatus comprising:

a processor interface configured to receive a data access directed for a heterogeneous memory system;

a plurality of storage device interfaces, each configured to communicate with at least one storage device of the heterogeneous memory system, and each storage device interface being associated with at least one performance characteristic,

wherein the heterogeneous memory system comprises a plurality of types of storage devices; and

a memory controller configured to;

locally route the data access from the processor interface to a one of the plurality of storage device interfaces based, at least in part, upon at least one performance characteristic associated with the one of the plurality of storage device interfaces.

27. The apparatus of claim 26, further comprising:

at least one accelerator processor configured to assist the memory controller route the data access from the processor interface to the one of the plurality of storage device interfaces.

28. The apparatus of claim 27, wherein the at least one accelerator processor includes an encryption circuit configured to encrypt at least a data portion of the data access before the data access is routed to the one of the plurality of storage device interfaces.

29. The apparatus of claim 27, wherein the at least one accelerator processor includes protocol translation circuit configured to translate the data access from a first communications protocol to a second communication protocol, before the data access is routed to the one of the plurality of storage device interfaces.

30. The apparatus of claim 27, wherein the at least one accelerator processor includes a cache organizer circuit configured to:

organize the heterogeneous memory system into a layered caching memory system,

maintain an inventory of the layered caching memory system, and

providing information regarding the layered caching memory system to the memory controller; and

wherein the memory controller is configured to select the one of the plurality of storage device interfaces based, at least in part, upon the information regarding the layered caching memory system provided by the cache organizer circuit.