Intelligent coded memory architecture with enhanced access scheduler
First Claim
1. A method for accessing data in a memory, comprising:
- determining, by a scheduler, a read pattern for reading data from memory to serve requests in a plurality of read bank queues, the memory comprising a plurality of memory banks and a plurality of coding banks, the coding banks storing a coded version of at least a portion of the data stored in the plurality of memory banks;
reading, by the scheduler, first data from a first memory bank of the memory banks;
reading, by the scheduler, coded data from a first coding bank of the coding banks;
accessing, by the scheduler, a status memory according to the reading the first data and the reading the coded data, the status memory denoting a status of a code for a section of the first memory bank, the status indicating whether the codes in the first coding bank are up to date with the data in the first memory bank, whether the codes are outdated and the data in the first memory bank is current, or whether the codes are outdated and data in the first coding bank is current; and
serving, by the scheduler, the first data or the coded data according to the status of the code denoted by the status memory.
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Accused Products
Abstract
A method, system, and architecture for efficiently accessing data in a memory shared by multiple processor cores that reduces the probability of bank conflicts and decreases latency is provided. In an embodiment, a method for accessing data in a memory includes determining, by a scheduler, a read pattern for reading data from memory to serve requests in a plurality of bank queues, the memory comprising a plurality of memory banks and a plurality of coding banks, the coding banks storing a coded version of at least some of the data stored in the plurality of memory banks; reading a first data from a first memory bank; reading coded data from one of the coding banks; and determining the second data according to the coded data and the first data.
37 Citations
25 Claims
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1. A method for accessing data in a memory, comprising:
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determining, by a scheduler, a read pattern for reading data from memory to serve requests in a plurality of read bank queues, the memory comprising a plurality of memory banks and a plurality of coding banks, the coding banks storing a coded version of at least a portion of the data stored in the plurality of memory banks; reading, by the scheduler, first data from a first memory bank of the memory banks; reading, by the scheduler, coded data from a first coding bank of the coding banks; accessing, by the scheduler, a status memory according to the reading the first data and the reading the coded data, the status memory denoting a status of a code for a section of the first memory bank, the status indicating whether the codes in the first coding bank are up to date with the data in the first memory bank, whether the codes are outdated and the data in the first memory bank is current, or whether the codes are outdated and data in the first coding bank is current; and serving, by the scheduler, the first data or the coded data according to the status of the code denoted by the status memory. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method in one or more master processors for accessing data in a memory, comprising:
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selecting a first element and a second element from a write bank queue; writing the first element to a memory bank; writing the second element to a coding bank as a coded memory element, wherein writing the first element to the memory bank performed in parallel with the writing the second element to the coding bank; and updating a status memory to indicate whether the first element and the second element are outdated, wherein updating the status memory comprises updating the status memory according to the writing the first element and the writing the second element, the status memory denoting a status of a code for a section of the memory bank, the status indicating whether the codes in the coding bank are up to date with the data in the memory bank, whether the codes are outdated and the data in the memory bank is current, or whether the codes are outdated and data in the coding bank is current.
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12. A data processing system, comprising:
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one or more master processors; and a non-transitory computer readable storage medium storing programming for execution by the master processors, the programming including instructions to; determine a read pattern for reading data from memory to serve requests in a plurality of read bank queues, the memory comprising a plurality of memory banks and a plurality of coding banks, the coding banks storing a coded version of at least a portion of the data stored in the plurality of memory banks; read first data from a first memory bank of the memory banks; read coded data from a first coding bank of the coding banks; access a status memory according to the reading the first data and the reading the coded data, the status memory denoting a status of a code for a section of the first memory bank, the status indicating whether the codes in the first coding bank are up to date with the data in the first memory bank, whether the codes are outdated and the data in the first memory bank is current, or whether the codes are outdated and data in the first coding bank is current; and serve the first data or the coded data according to the status of the code denoted by the status memory. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
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21. A processor, comprising:
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a plurality of master core processors; a coded memory controller comprising a plurality of bank queues and an access scheduler; a memory comprising a plurality of memory banks and a plurality of coding banks, the coding banks comprising coded data of at least a part of the data in the memory banks; and a status memory maintained by the access scheduler, wherein the status memory is configured to indicate whether data in a memory bank and a coding bank are outdated, wherein the status memory further is further configured to indicate whether the data in the memory bank and the coding bank are up to date, wherein the bank queues comprise a list of read requests and write requests, wherein the access scheduler searches the bank queues and schedules read operations from the memory such that a read operation from a memory bank corresponding to a first read request enables obtaining data from one of the coding banks that satisfies a second read request, and wherein the access scheduler obtains two entries from a write bank queue and writes a first entry to one of the memory banks and writes a second entry to one of the coding banks as a coded data entry. - View Dependent Claims (22, 23, 24, 25)
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Specification