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Method of processing incomplete memory operations in a memory device during a power up sequence and a power down sequence using a dynamic redundancy register

  • US 10,437,491 B2
  • Filed: 12/27/2017
  • Issued: 10/08/2019
  • Est. Priority Date: 09/27/2016
  • Status: Active Grant
First Claim
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1. A method of writing data into a memory device, the method comprising:

  • utilizing a pipeline to process write operations of a first plurality of data words addressed to a memory bank;

    writing a second plurality of data words and associated memory addresses into a cache memory, wherein said cache memory is associated with said memory bank and wherein further each data word of said second plurality of data words is either awaiting write verification associated with said memory bank or is to be re-written into said memory bank;

    detecting a power down signal;

    responsive to the power down signal, transferring the second plurality of data words and associated memory addresses from said cache memory into a secure memory storage area reserved in the memory bank; and

    powering down the memory device.

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