Techniques for non-volatile memory page retirement

• US 10,437,512 B2
• Filed: 12/29/2016
• Issued: 10/08/2019
• Est. Priority Date: 12/29/2016
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Zhu, Feng, Madraswala, Aliasgar S., Guo, Xin
• Primary Examiner(s): Hur, J. H.
• Application Number:
  US15/394,261
• Publication Number:
  US 20180189154A1
• Time in Patent Office: 1,013 Days
• Field of Search: None
• CPC Class Codes: G06F 11/0727 in a storage system, e.g. in a DASD or network based storage system drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 11/1428 with loss of hardware functionality
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators

Abstract

Examples herein include techniques for flash page retirement following one or more defects in nonvolatile memory. In some examples, a storage controller may retire a first logical page in response to a first read error, and write data to the one or more NVM devices in a program-erase (P/E) cycle without a dummy page being programmed or generated for the retired first logical page. The storage controller may further retire a second logical page in response to a second read error, wherein the first logical page has a higher order than the second logical page in a same physical memory page.

Claims

1. An apparatus comprising:

one or more non-volatile memory (NVM) devices, the one or more NVM devices to comprise triple level cell (TLC) NVM devices; and

a storage controller that includes logic, at least a portion of which is in hardware, the logic configured to;

retire a first logical page in response to a first read error;

preclude a dummy page from being generated for the retired first logical page;

write data to the one or more NVM devices in a program-erase (P/E) cycle;

retire a second logical page in response to a second read error, wherein the first logical page has a higher order than the second logical page in a same physical memory page;

preclude a dummy page from being generated for the retired second logical page;

write data to the one or more NVM devices in a second P/E cycle;

retire a third logical page in response to a third read error;

program a dummy page for the retired third logical page; and

write data to the one or more NVM devices in a third P/E cycle following programming of the dummy page for the retired third logical page.

2. The apparatus of claim 1, the first, second, and third logical pages located in the same physical memory page.

3. The apparatus of claim 1, the second logical page having a higher order than the third logical page for the same physical memory page.

4. The apparatus of claim 1, wherein the logic is further configured to program the second logical page with shifted program verify voltages.

5. The apparatus of claim 1, wherein the logic is further configured to program the third logical page with shifted program verify voltages.

6. The apparatus of claim 1, wherein the logic is further configured to:

program a dummy page for the retired second logical page; and

write data to the one or more NVM devices in a second P/E cycle following programming of the dummy page for the retired second logical page.

7. The apparatus of claim 1, the first logical page being an extra page, and the second logical page being an upper page or a lower page.

8. The apparatus of claim 1, the one or more NVM devices comprises one or more types of non-volatile memory to include 3-dimensional cross-point memory, flash memory, ferroelectric memory, silicon-oxide-nitride-oxide-silicon (SONOS) memory, polymer memory, ferroelectric polymer memory, ferroelectric transistor random access memory (FeTRAM or FeRAM), ovonic memory, nanowire, electrically erasable programmable read-only memory (EEPROM), phase change memory, memristors or spin transfer torque-magnetoresistive random access memory (STT-MRAM).

9. A method comprising:

receiving, at a controller for one or more non-volatile memory (NVM) devices, a read request, the NVM devices comprising triple level cell (TLC) devices;

retiring a first logical page in response to a first read error;

precluding a dummy page from being generated for the retired first logical page;

writing data to the one or more NVM devices in a program-erase (P/E) cycle; and

retiring a second logical page in response to a second read error, wherein the first logical page has a higher order than the second logical page in a same physical memory page;

precluding a dummy page from being generated for the retired second logical page;

writing data to the one or more NVM devices in a second P/E cycle;

retiring a third logical page in response to a third read error;

programming a dummy page for the retired third logical page; and

writing data to the one or more NVM devices in a third P/E cycle following programming of the dummy page for the retired third logical page.

10. The method of claim 9, further comprising programming the third logical page with shifted program verify voltages.

11. The method of claim 9, further comprising programming the second logical page with shifted program verify voltages.

12. A system comprising:

a storage system including;

one or more non-volatile memory (NVM) devices, the one or more NVM devices to comprise triple level cell (TLC) NVM devices;

and

a storage controller that includes logic, at least a portion of which is in hardware, the logic configured to;

retire a first logical page in response to a first read error;

preclude a dummy page from being generated for the retired first logical page;

write data to the one or more NVM devices in a program-erase (P/E) cycle;

retire a second logical page in response to a second read error, wherein the first logical page has a higher order than the second logical page in a same physical memory page;

preclude a dummy page from being generated for the retired second logical page;

write data to the one or more NVM devices in a second P/E cycle;

retire a third logical page in response to a third read error;

program a dummy page for the retired third logical page; and

write data to the one or more NVM devices in a third P/E cycle following programming of the dummy page for the retired third logical page.

13. The system of claim 12, the first, second, and third logical pages being located in the same physical memory page.

14. The system of claim 12, the second logical page having a higher order than the third logical page for the same physical memory page.

15. The system of claim 12, wherein the logic is further configured to program the second logical page and the third logical page with shifted program verify voltages.

16. The system of claim 12, further comprising a processor for a host computing device to execute one or more applications.

17. The system of claim 12, wherein the logic is further configured to perform a defect management policy to the one or more NVM devices to retire the same physical memory page corresponding to the first and second logical pages.

18. The system of claim 12, the first logical page being an extra page, and the second logical page being an upper page or a lower page.

19. The system of claim 12, the one or more NVM devices comprising one or more types of non-volatile memory to include 3-dimensional cross-point memory, flash memory, ferroelectric memory, silicon-oxide-nitride-oxide-silicon (SONOS) memory, polymer memory, ferroelectric polymer memory, ferroelectric transistor random access memory (FeTRAM or FeRAM), ovonic memory, nanowire, electrically erasable programmable read-only memory (EEPROM), phase change memory, memristors or spin transfer torque-magnetoresistive random access memory (STT-MRAM).

20. The system of claim 12, comprising one or more of:

one or more processors communicatively coupled to the storage controller;

a network interface communicatively coupled to the system;

a battery coupled to the system;

or

a display communicatively coupled to the system.