Systems and methods for latency based data recycling in a solid state memory system

• US 10,437,513 B2
• Filed: 07/25/2017
• Issued: 10/08/2019
• Est. Priority Date: 10/17/2013
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Cai, Yu, Wu, Yunxiang, Chen, Ning, Haratsch, Erich F., Chen, Zhengang
• Primary Examiner(s): Padmanabhan, Mano
• Assistant Examiner(s): Baughman, William E.
• Application Number:
  US15/659,267
• Publication Number:
  US 20170322750A1
• Time in Patent Office: 805 Days
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0653 Monitoring storage devices or systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: H03M 13/1102 Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
• CPC Class Codes: H03M 13/1105 Decoding
• CPC Class Codes: H03M 13/1111 Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
• CPC Class Codes: H03M 13/1128 Judging correct decoding and iterative stopping criteria other than syndrome check and upper limit for decoding iterations
• CPC Class Codes: H03M 13/3746 with iterative decoding
• CPC Class Codes: H03M 13/6505 Memory efficient implementations

Abstract

Systems and method relating generally to solid state memory, and more particularly to systems and methods for recycling data in a solid state memory. The systems and methods include receiving a data set maintained in a memory device, applying at least one iteration of a data decoding algorithm to the data set by a data decoder circuit to yield a decoded output, counting the number of iterations of the data decoding algorithm applied to the data set to yield an iteration count, and recycling the data set to the memory device. The recycling is triggered based at least in part on the iteration count.

Claims

1. A data processing system, comprising:

a memory device operable to maintain a data set;

a data decoder circuit operable to determine a decoded output based on the data set and provide an iteration count indicating a number of iterations that a data decoding algorithm is applied to the data set; and

a recycle control circuit operable to compare a frequency of access corresponding to the data set with an access frequency threshold, compare the iteration count to a first iteration threshold when the frequency of access satisfies the access frequency threshold, compare the iteration count to a second iteration threshold different from the first iteration threshold when the frequency of access fails to satisfy the access frequency threshold, and recycle read data corresponding to the data set upon determining the iteration count satisfies the first or second iteration threshold.

2. The data processing system of claim 1, wherein the data decoder circuit determines the decoded output by applying one or more iterations of the data decoding algorithm to the data set.

3. The data processing system of claim 1, wherein the data decoding algorithm includes at least a low density parity check decoding algorithm.

4. The data processing system of claim 1, further comprising a memory access circuit operable to calculate the frequency of access corresponding to the data set.

5. The data processing system of claim 4, wherein the memory access circuit is operable to access the data set from the memory device, and the recycle is triggered based at least in part on at least one of the iteration count and the frequency of access.

6. The data processing system of claim 1, wherein at least one of the first iteration threshold, the second iteration threshold, and the access frequency threshold, or any combination thereof, is user programmable.

7. The data processing system of claim 1, wherein at least one of the data decoder circuit and the recycle control circuit are incorporated in an integrated circuit.

8. The data processing system of claim 1, wherein the data processing system is implemented on an integrated circuit.

9. The data processing system of claim 1, wherein the memory device includes at least a flash memory device.

10. The data processing system of claim 9, wherein the flash memory device is able to hold multiple bits of data in each memory cell of the flash memory device.

11. A method for data recycling control in a memory device, the method comprising:

receiving a data set maintained in a memory device;

applying at least one iteration of a data decoding algorithm to the data set;

counting the number of iterations of the data decoding algorithm applied to the data set to yield an iteration count;

comparing, by a recycle control circuit, a frequency of access corresponding to the data set with an access frequency threshold;

comparing, by the recycle control circuit, the iteration count to a first iteration threshold when the frequency of access satisfies the access frequency threshold;

comparing, by the recycle control circuit, the iteration count to a second iteration threshold different from the first iteration threshold when the frequency of access fails to satisfy the access frequency threshold; and

recycling, by the recycle control circuit, read data corresponding to the data set upon determining the iteration count satisfies the first or second iteration threshold.

12. The method of claim 11, wherein the data decoding algorithm includes at least a low density parity check decoding algorithm.

13. The method of claim 11, further comprising:

calculating the frequency of access corresponding to the data set; and

determining the frequency of access corresponding to the data set exceeds the access frequency threshold.

14. The method of claim 11, wherein the recycle is triggered based at least in part on at least one of the iteration count and the frequency of access.

15. The method of claim 11, further comprising:

operating a data decoder circuit to apply at least one iteration of the data decoding algorithm to the data set to yield a decoded output.

16. The method of claim 11, wherein the method further comprises:

programming at least one of the first iteration threshold, the second iteration threshold, and the access frequency threshold, or any combination thereof.

17. A data storage device, the data storage device comprising:

a flash memory device operable to maintain a data set;

a memory access circuit operable to;

access the data set from the memory device; and

calculate a frequency of access corresponding to the data set;

a data decoder circuit operable to apply one or more iterations of a data decoding algorithm to the data set, and to provide an iteration count indicating a number of iterations that the data decoding algorithm was applied to the data set; and

a recycle control circuit operable to compare a frequency of access corresponding to the data set with an access frequency threshold, compare the iteration count to a first iteration threshold when the frequency of access satisfies the access frequency threshold, compare the iteration count to a second iteration threshold different from the first iteration threshold when the frequency of access fails to satisfy the access frequency threshold, and recycle read data corresponding to the data set upon determining the iteration count satisfies the first or second iteration threshold.

18. The data storage device of claim 17, wherein the data decoder circuit determines the decoded output by applying one or more iterations of the data decoding algorithm to the data set.

19. The data storage device of claim 17, wherein the data decoding algorithm includes at least a low density parity check decoding algorithm.

20. The data storage device of claim 17, wherein the memory access circuit is operable to access the data set from the memory device, and the recycle is triggered based at least in part on at least one of the iteration count and the frequency of access.