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Server-enabled chip card interface tamper detection

  • US 10,438,189 B2
  • Filed: 02/22/2017
  • Issued: 10/08/2019
  • Est. Priority Date: 02/22/2017
  • Status: Active Grant
First Claim
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1. A payment reader for exchanging payment information with a chip card and having circuitry to identify an attempt to tamper with a chip card interface of the payment reader, comprising:

  • a chip card interface comprising at least a voltage interface, a reset interface, a clock interface, an input/output interface, a ground interface, and a programming interface;

    a plurality of chip card lines, comprising;

    a voltage line coupled to the voltage interface;

    a reset line coupled to the reset interface;

    a clock line coupled to the clock interface;

    an input/output line coupled to the input/output interface;

    a ground line coupled to the ground interface; and

    a programming line coupled to the programming interface; and

    a communication interface;

    a memory having instructions stored thereon;

    a processing unit coupled to the chip card interface via the plurality of chip card lines, coupled to the communication interface, and coupled to the memory to execute instructions to;

    apply a non-standard signal to one or more of the plurality of chip card lines;

    measure a response value for the non-standard signal;

    transmit the response value to a payment service system via the communication interface;

    determine whether one or more local tamper criteria are satisfied based on the response value, wherein the one or more local tamper criteria are based on one or more communications received from the payment service system; and

    identify a tamper attempt when the one or more local tamper criteria are satisfied.

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