Multi-phase clock division
First Claim
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1. A semiconductor device comprising:
- memory;
a command interface configured to receive a write command to write data to the memory;
a data strobe pin configured to receive a data strobe to assist in writing the data to the memory;
phase division circuitry configured to divide the data strobe into a plurality of phases to be used in writing the data to the memory, wherein pairs of phases of the plurality of phases correspond to corresponding rising and falling edges of the data strobe, and a first phase of the plurality of phases corresponds to rising edges of a first set of pulses of the data strobe, a second phase of the plurality of phases corresponds to falling edges of the first set of pulses of the data strobe, a third phase of the plurality of phases corresponds to rising edges of a second set of pulses of the data strobe, wherein each pulse of the second set of pulses occurs between two pulses of the first set of pulses, and a fourth phase of the plurality of phases corresponds to falling edges of the second set of pulses of the data strobe; and
selection circuitry configured to output a signal based at least in part on which phase of the plurality of phases is currently capturing a write command.
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Abstract
Devices and methods include receiving write command at a command interface of the semiconductor device to write data to memory. An external data strobe is received at a data strobe pin of the semiconductor device. The received external data strobe is divided into multiple phases using phase division circuitry to divide the data strobe into multiple phases to be used in writing the data to the memory.
14 Citations
17 Claims
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1. A semiconductor device comprising:
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memory; a command interface configured to receive a write command to write data to the memory; a data strobe pin configured to receive a data strobe to assist in writing the data to the memory; phase division circuitry configured to divide the data strobe into a plurality of phases to be used in writing the data to the memory, wherein pairs of phases of the plurality of phases correspond to corresponding rising and falling edges of the data strobe, and a first phase of the plurality of phases corresponds to rising edges of a first set of pulses of the data strobe, a second phase of the plurality of phases corresponds to falling edges of the first set of pulses of the data strobe, a third phase of the plurality of phases corresponds to rising edges of a second set of pulses of the data strobe, wherein each pulse of the second set of pulses occurs between two pulses of the first set of pulses, and a fourth phase of the plurality of phases corresponds to falling edges of the second set of pulses of the data strobe; and selection circuitry configured to output a signal based at least in part on which phase of the plurality of phases is currently capturing a write command. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A semiconductor device comprising:
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memory; a command interface configured to receive a write command to write data to the memory; a data strobe pin configured to receive a data strobe to assist in writing the data to the memory; and phase division circuitry configured to divide the data strobe into a plurality of phases to be used in writing the data to the memory, wherein pairs of phases of the plurality of phases correspond to corresponding rising and falling edges of the data strobe wherein a first phase of the plurality of phases corresponds to rising edges of a first set of pulses of the data strobe; a second phase of the plurality of phases corresponds to falling edges of the first set of pulses of the data strobe; a third phase of the plurality of phases corresponds to rising edges of a second set of pulses of the data strobe, wherein each pulse of the second set of pulses occurs between two pulses of the first set of pulses; and a fourth phase of the plurality of phases corresponds to falling edges of the second set of pulses of the data strobe, wherein the phase division circuitry comprises a channel for each phase of the plurality of phases, and wherein half of the channels include count detection circuitry. - View Dependent Claims (10, 11)
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12. A memory device comprising:
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memory; a command interface configured to receive a write command to write data to the memory; a data strobe pin configured to receive an external data strobe to assist in writing the data to the memory; phase division circuitry configured to divide the data strobe into a plurality of phases to be used in writing the data to the memory, wherein the phase division circuitry comprises; delay circuitry; bypass routing configured to bypass the delayed circuitry; phase detection circuitry configured to identify which phase of the plurality of phases received a pulse of the data strobe first; and output circuitry configured to selectively output data indicative of an identified phase using the delay circuitry or the bypass routing. - View Dependent Claims (13, 14, 15, 16, 17)
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Specification