Dual channel FinFETs having uniform fin heights

• US 10,438,855 B2
• Filed: 02/17/2017
• Issued: 10/08/2019
• Est. Priority Date: 02/17/2017
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bi, Zhenxing, Cheng, Kangguo, Xu, Peng, Yang, Jie
• Primary Examiner(s): Niesz, Jamie C
• Application Number:
  US15/435,627
• Publication Number:
  US 20180240713A1
• Time in Patent Office: 963 Days
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/20 Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
• CPC Class Codes: H01L 21/2205 from the substrate during epitaxy, e.g. autodoping; Preventing or using autodoping
• CPC Class Codes: H01L 21/2236 from or into a plasma phase
• CPC Class Codes: H01L 21/2251 Diffusion into or out of group IV semiconductors
• CPC Class Codes: H01L 21/228 using diffusion into or out of a solid from or into a liquid phase, e.g. alloy diffusion processes H01L21/221 - H01L21/222 take precedence
• CPC Class Codes: H01L 21/2652 Through-implantation
• CPC Class Codes: H01L 21/30608 Anisotropic liquid etching H01L21/3063 takes precedence
• CPC Class Codes: H01L 21/308 using masks H01L21/3063, H01L21/3065 take precedence
• CPC Class Codes: H01L 21/3085 characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/8213 the substrate being a semiconductor, using SiC technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/8252 the substrate being a semiconductor, using III-V technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/8254 the substrate being a semiconductor, using II-VI technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/8256 the substrate being a semiconductor, using technologies not covered by one of groups H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252 and H01L21/8254 H01L21/8258 takes precedence
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 : including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/161 : including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/36 : characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/66795 : with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/6681 : using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7854 : with rounded corners

Abstract

A method of making a semiconductor device including forming a first blanket layer on a substrate; forming a second blanket layer on the first blanket layer; patterning a first fin of a first transistor region and a second fin of a second transistor region in the first blanket layer and the second blanket layer; depositing a mask on the second transistor region; removing the first fin to form a trench; growing a first semiconductor layer in the trench where the first fin was removed; and growing a second semiconductor layer on the first semiconductor layer.

Claims

1. A semiconductor device comprising:

a n-type field effect transistor (NFET) comprising a plurality of first fins extending from a substrate, each of the plurality of first fins comprising an p-doped silicon portion extending from the substrate and a portion consisting of silicon extending directly from the p-doped silicon portion, the p-doped silicon portion of each of the plurality of first fins having a rounded bottom edge, and the p-doped silicon portion being a single discrete layer of silicon doped with a p-type dopant; and

a p-type field effect transistor (PFET) comprising a plurality of second fins extending from the substrate, each of the plurality of second fins comprising an n-doped silicon portion extending from the substrate and a portion consisting of silicon germanium extending directly from the n-doped silicon portion, the n-doped silicon portion of each of the plurality of second fins having a substantially flat bottom edge, and the n-doped silicon portion being a single discrete layer of silicon doped with an n-type dopant.

2. The semiconductor device of claim 1, wherein the n-doped silicon portion of the plurality of second fins has a thickness of about 20 to about 60 nanometers.

3. The semiconductor device of claim 1, wherein the portion consisting of silicon germanium of each of the plurality of second fins has a thickness of about 20 to about 60 nanometers.

4. The semiconductor device of claim 1, wherein the p-type dopant is boron.

5. The semiconductor device of claim 1, wherein the p-type dopant is gallium.

6. The semiconductor device of claim 1, wherein the p-type dopant is indium.

7. The semiconductor device of claim 1, wherein the substrate comprises silicon.