Power quad flat no-lead (PQFN) package in a single shunt inverter circuit

• US 10,438,876 B2
• Filed: 04/25/2017
• Issued: 10/08/2019
• Est. Priority Date: 12/13/2010
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Inventors: Fernando, Dean, Barbosa, Roel, Takahashi, Toshio
• Primary Examiner(s): Gumedzoe, Peniel M
• Application Number:
  US15/496,951
• Publication Number:
  US 20170229383A1
• Time in Patent Office: 896 Days
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/29101 the principal constituent melting at a temperature of less than 400°C
• CPC Class Codes: H01L 2224/2929 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/29339 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4903 Connectors having different sizes, e.g. different diameters
• CPC Class Codes: H01L 2224/49111 the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 2224/49113 the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/49513 having bonding material between chip and die pad
• CPC Class Codes: H01L 23/4952 : the additional leads being a bump or a wire
• CPC Class Codes: H01L 23/49541 : Geometry of the lead-frame
• CPC Class Codes: H01L 23/49548 : Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 23/49562 : for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/49575 : Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/49582 : Metallic layers on lead frames
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0781 : being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13064 : High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18301 : being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
• CPC Class Codes: H01L 2924/20753 : larger or equal to 30 microns less than 40 microns
• CPC Class Codes: H01L 2924/20755 : larger or equal to 50 microns less than 60 microns
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/30111 : matching
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

According to an exemplary implementation, a power quad flat no-lead (PQFN) package includes a driver integrated circuit (IC) situated on a leadframe. The PQFN package further includes low-side U-phase, low-side V-phase, and low-side W-phase power switches situated on the leadframe. A logic ground of the leadframe is coupled to a support logic circuit of the driver IC. A power stage ground of the leadframe is coupled to sources of the low-side U-phase, low-side V-phase, and low-side W-phase power switches. The power stage ground can further be coupled to gate drivers of the driver IC.

Claims

1. A power quad flat no-lead (PQFN) package comprising:

a leadframe; and

a driver integrated circuit (IC) positioned to a driver IC die pad of the leadframe, wherein the driver IC comprises;

a first level shifter configured to output;

a first signal to a first gate driver to drive a first high-side power transistor of a bridge circuit of the PQFN package; and

a second signal to a second gate driver to drive a second high-side power transistor of a bridge circuit of the PQFN package, wherein the first high-side power transistor and the second high-side power transistor are situated on a top-side of a common die pad; and

a second level shifter configured to output;

a third signal to a third gate driver of the driver IC to drive a first low-side power transistor of the bridge circuit of the PQFN package,

wherein a drain of the first low-side power transistor is situated on a first die pad, and the first die pad is electrically connected to a first leadframe strip comprising a first leadframe island, and

wherein at least a portion of the first leadframe strip is exposed at an edge of the leadframe; and

a fourth signal to a fourth gate driver of the driver IC to drive a second low-side power transistor of the bridge circuit of the PQFN package,

wherein a drain of the second low-side power transistor is situated on a second die pad, and the second die pad is electrically connected to a second leadframe strip comprising a second leadframe island, and

wherein at least a portion of the second leadframe strip is exposed at the edge of the leadframe.

2. The (PQFN) package of claim 1, wherein the driver IC further comprises input logic:

coupled to the first level shifter to control the first level shifter to output the first signal to the first gate driver to drive the first high-side power transistor of the bridge circuit of the PQFN package; and

coupled to the second level shifter to control the second level shifter to output the third signal to the third gate driver to drive the first low-side power transistor of the bridge circuit of the PQFN package.

3. The (PQFN) package of claim 1, wherein the driver IC further comprises an undervoltage protection circuit configured to detect a supply voltage undervoltage condition to disable switching of the bridge circuit.

4. The (PQFN) package of claim 1, wherein the driver IC further comprises an overcurrent protection circuit configured to output a signal indicative of an overcurrent condition to disable switching of the bridge circuit.

5. The (PQFN) package of claim 4, wherein the first level shifter is configured to output the signal to the first gate driver at magnitude greater than the second level shifter is configured to output the third signal to the third gate driver.

6. The (PQFN) package of claim 1, wherein the first high-side power transistor corresponds to one of a V-phase power switch, a V-phase power switch and a W-phase power switch of the bridge circuit.

7. The (PQFN) package of claim 1, wherein the first low-side power transistor corresponds to one of a U-phase power switch, a V-phase power switch and a W-phase power switch of the bridge circuit.

8. The (PQFN) package of claim 1, wherein at least one of the first high-side power transistor, the second high-side power transistor, the first low-side power transistor, and the second low-side power transistor corresponds to a fast-reverse epitaxial diode field-effect transistor (FREDFET).

9. The (PQFN) package of claim 1, wherein at least one of the first high-side power transistor, the second high-side power transistor, the first low-side power transistor, and the second low-side power transistor corresponds to an insulated-gate bipolar transistor (IGBTs).

10. The (PQFN) package of claim 1, wherein at least one of the first high-side power transistor, the second high-side power transistor, the first low-side power transistor, and the second low-side power transistor corresponds to a group III-V transistor.

11. A power quad flat no-lead (PQFN) package comprising:

a leadframe;

a common die pad; and

a U-phase power switch, a V-phase power switch, a W-phase power switch, and a driver IC (Integrated Circuit) each positioned to the leadframe, wherein the U-phase power switch, the V-phase power switch, the W-phase power switch are each situated respectively on a first, second and third die pad different from the common die pad,

wherein the driver IC comprises a first level shifter configured to;

output a first signal to a first gate driver to drive the U-phase power switch, wherein the first die pad is electrically connected to a first leadframe strip comprising a first leadframe island;

output a second signal to a second gate driver to drive the V-phase power switch,

wherein the second die pad is electrically connected to a second leadframe strip comprising a second leadframe island; and

output a third signal to a third gate driver to drive the W-phase power switch.

12. The (PQFN) package of claim 11, wherein at least one of the U-phase power switch, the V-phase power switch, and the W-phase power switch corresponds to a low-side power switch of a bridge circuit of the PQFN package.

13. The (PQFN) package of claim 11, further comprising:

a second level shifter; and

a second U-phase power switch, a second V-phase power switch, and a second W-phase power switch, wherein;

the second U-phase power switch, the second V-phase power switch, and the second W-phase power switch are each situated on the common die pad,

a second level shifter configured to;

output a fourth signal to a fourth gate driver to drive the U-phase power switch;

output a fifth signal to a fifth gate driver to drive the U-phase power switch; and

output a sixth signal to a sixth gate driver to drive the U-phase power switch; and

at least one of the second U-phase power switch, the second V-phase power switch, and the second W-phase power switch corresponds to a high-side power switch of a bridge circuit of the PQFN package.

14. The (PQFN) package of claim 11, wherein the driver IC further comprises an undervoltage protection circuit configured to detect a supply voltage undervoltage condition to disable switching of a bridge circuit of the PQFN package that comprises the U-phase power switch, the V-phase power switch, and the W-phase power switch.

15. The (PQFN) package of claim 11, wherein the driver IC further comprises an overcurrent protection circuit configured to output a signal indicative of an overcurrent condition to disable switching of a bridge circuit of the PQFN package that comprises the U-phase power switch, the V-phase power switch, and the W-phase power switch.

16. The (PQFN) package of claim 11, wherein at least one of the U-phase power switch, the V-phase power switch, and the W-phase power switch corresponds to a fast-reverse epitaxial diode field-effect transistor (FREDFET).

17. The (PQFN) package of claim 11, wherein at least one of the U-phase power switch, the V-phase power switch, and the W-phase power switch corresponds to an insulated-gate bipolar transistor (IGBTs).

18. The (PQFN) package of claim 11, wherein at least one of the U-phase power switch, the V-phase power switch, and the W-phase power switch corresponds to a group III-V transistor.