Semiconductor device and manufacturing method thereof

• US 10,438,965 B2
• Filed: 10/30/2017
• Issued: 10/08/2019
• Est. Priority Date: 12/22/2014
• Status: Active Grant

• Current Assignee: ASM IP Holding B.V. (ASM International NV)
• Original Assignee: ASM IP Holding B.V. (ASM International NV)
• Inventors: Kim, Young Jae, Choi, Seung Woo, Yoo, Yong Min
• Primary Examiner(s): Wright, Tucker J
• Assistant Examiner(s): Baptiste, Wilner Jean
• Application Number:
  US15/798,150
• Publication Number:
  US 20180069019A1
• Time in Patent Office: 708 Days
• CPC Class Codes: H01L 21/2255 the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

Disclosed are a semiconductor device and a manufacturing method thereof. According to the semiconductor device and the manufacturing method thereof according to exemplary embodiments of the present invention, after the dopant source layer is uniformly deposited on a channel layer of the device with the 3-dimensional vertical structure by the plasma-enhanced atomic layer deposition (PEALD) method, the deposited dopant source layer is heat-treated so that the dopants are diffused into the channel layer to function as charge carriers, thereby preventing the charges in the channel layer from being reduced. According to the exemplary embodiments of the present invention, the diffusion speed and concentration of the dopant may be controlled by forming the barrier layer between the channel layer and the dopant source layer.

Claims

1. A semiconductor device, comprising:

a structure in which a gate layer and an interlayer insulation layer are alternately stacked;

a non-conductive layer formed at a lateral surface of the structure;

a channel layer formed at a lateral surface of the non-conductive layer;

a barrier layer formed at a lateral surface of the channel layer; and

a source layer formed at a lateral surface of the barrier layer;

wherein the source layer contains phosphorus elements.

2. The semiconductor device of claim 1, wherein the source layer is a phosphosilicate glass (PSG) layer.

3. The semiconductor device of claim 1, wherein the non-conductive layer is an oxide-nitride-oxide (ONO) layer.

4. The semiconductor device of claim 1, wherein the barrier layer is a silicon oxide layer.

5. The semiconductor device of claim 1, wherein the channel layer is a polysilicon layer.

6. The semiconductor device of claim 1, further comprising a capping layer formed at a lateral surface of the source layer.

7. The semiconductor device of claim 6, wherein the barrier layer and the capping layer are silicon oxide layers.

8. The semiconductor device of claim 7, wherein the barrier layer and the capping layer are silicon oxide layers having different film qualities or different thicknesses.