Cross-point memory and methods for fabrication of same

• US 10,439,001 B2
• Filed: 12/29/2017
• Issued: 10/08/2019
• Est. Priority Date: 02/25/2014
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Sciarrillo, Samuele
• Primary Examiner(s): Luke, Daniel
• Application Number:
  US15/858,811
• Publication Number:
  US 20180138242A1
• Time in Patent Office: 648 Days
• CPC Class Codes: H10B 63/24 of the Ovonic threshold switching type
• CPC Class Codes: H10B 63/32 of the bipolar type
• CPC Class Codes: H10B 63/34 of the vertical channel field-effect transistor type
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/882 Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
• CPC Class Codes: H10N 70/8822 Sulfides, e.g. CuS
• CPC Class Codes: H10N 70/8825 Selenides, e.g. GeSe
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe

Abstract

The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a memory device of the memory array comprises a substrate and a memory cell stack formed between and electrically connected to first and second conductive lines. The memory cell stack comprises a first memory element over the substrate and a second memory element formed over the first element, wherein one of the first and second memory elements comprises a storage element and the other of the first and second memory elements comprises a selector element. The memory cell stack additionally comprises a first pair of sidewalls opposing each other and a second pair of sidewalls opposing each other and intersecting the first pair of sidewalls. The memory device additionally comprises first protective dielectric insulating materials formed on a lower portion of the first pair of sidewalls and an isolation dielectric formed on the first protective dielectric insulating material and further formed on an upper portion of the first pair of sidewalls.

Claims

1. A memory array, comprising:

a substrate;

a plurality of memory cell stacks formed across the substrate, each of the memory cell stacks comprising;

a first pair of opposing sidewalls extending in a first direction;

a second pair of opposing sidewalls extending in a second direction and opposing each other;

a first dielectric material formed on the first pair of opposing sidewalls, the first dielectric material in contact with a selector element material and extending from a first electrode material to and in contact with a second electrode material, the first electrode material above the substrate, the selector element material in contact with the first electrode material, the second electrode material in contact with the selector element material;

a second dielectric material formed on at least a portion of the second pair of opposing sidewalls, the second dielectric material in contact with the selector element material and extending from the first electrode material to and in contact with the second electrode material, the second dielectric material in contact with a portion of an upper surface of the first dielectric material and an upper surface of an isolation dielectric in contact with the first dielectric material;

a storage element material in contact with the second electrode material; and

a third electrode material in contact with the storage element material.

2. The memory array of claim 1, wherein the first dielectric material and the second dielectric material surround the selector element material.

3. The memory array of claim 2, wherein the first dielectric material and the second dielectric material surround the selector element material based at least in part on the first dielectric material being formed on a first pair of sidewalls of the selector element material and the second dielectric material being formed on a second pair of sidewalls of the selector element material.

4. The memory array of claim 1, wherein the second dielectric material is in contact with an upper surface of the first electrode material.