Semiconductor device and method of manufacturing same

• US 10,439,032 B2
• Filed: 05/14/2018
• Issued: 10/08/2019
• Est. Priority Date: 06/22/2017
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Yoshitomi, Atsushi, Kawashima, Yoshiyuki
• Primary Examiner(s): Taylor, Earl N
• Application Number:
  US15/978,296
• Publication Number:
  US 20180374924A1
• Time in Patent Office: 512 Days
• CPC Class Codes: H01L 29/4234 Gate electrodes for transistors with charge trapping gate insulator
• CPC Class Codes: H01L 29/42344 with at least one additional gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7856 with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides H01L29/7855 takes precedence
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 43/30 characterised by the memory core region

Abstract

To provide a semiconductor device having improved reliability by relaxing the unevenness of the injection distribution of electrons and holes into a charge accumulation film attributable to the shape of the fin of a MONOS memory comprised of a fin transistor. Of a memory gate electrode configuring a memory cell formed above a fin, a portion contiguous to an ONO film that covers the upper surface of the fin and a portion contiguous to the ONO film that covers the side surface of the fin are made of electrode materials different in work function, respectively, and the boundary surface between them is located below the upper surface of the fin.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

a protruding semiconductor layer which is a portion of the semiconductor substrate, protrudes from a main surface of the semiconductor substrate, and extends in a first direction along the main surface;

a gate electrode adjacent to an upper surface and a side surface of the protruding semiconductor layer via an insulating film including a charge accumulation film and extending in a second direction crossing the first direction; and

a source region and a drain region sandwiching the gate electrode therebetween in the first direction of the protruding semiconductor layer,

wherein the gate electrode has

     1) a first gate electrode adjacent to the side surface of the protruding semiconductor layer via the insulating film and in contact with the insulating film positioned on the side surface of the protruding semiconductor layer and

     2) a second gate electrode adjacent to the upper surface of the protruding semiconductor layer via the insulating film and in contact with the insulating film positioned on the upper surface of the protruding semiconductor layer,

wherein the first gate electrode and the second gate electrode include respectively different electrode materials,

wherein a boundary surface between the first gate electrode and the second gate electrode lies on the side of the main surface with respect to the upper surface of the protruding semiconductor layer, and

wherein the electrode material of the second gate electrode has a work function higher than that of the electrode material of the first gate electrode.

2. The semiconductor device according to claim 1,

wherein the electrode material of the first gate electrode is polysilicon, and

wherein the electrode material of the second gate electrode is any of Al, Ti, Ta, Ru, W, and alloy materials containing any of Al, Ti, Ta, Ru, and W.

3. The semiconductor device according to claim 2, wherein the first gate electrode and the second gate electrode have therebetween a barrier metal.

4. The semiconductor device according to claim 1,

wherein the electrode material of the first gate electrode is polysilicon, and

wherein the electrode material of the second gate electrode is a metal silicide.

5. The semiconductor device according to claim 4,

wherein the first gate electrode and the second gate electrode have therebetween a silicon oxide film.

6. The semiconductor device according to claim 1, wherein the respective electrode materials of the first gate electrode and the second gate electrode are each any of Al, Ti, Ta, Ru, W, and alloy materials containing any of Al, Ti, Ta, Ru, and W.

7. The semiconductor device according to claim 2, wherein the first gate electrode and the second gate electrode have therebetween a work function control film including TaN or TiN.

8. The semiconductor device according to claim 7, wherein the first gate electrode and the work function control film and the second gate electrode and the work function control film each have therebetween a barrier metal.

9. A semiconductor device comprising:

a semiconductor substrate;

a protruding semiconductor layer which is a portion of the semiconductor substrate, protrudes from a main surface of the semiconductor substrate, and extends in a first direction along the main surface;

a memory gate electrode adjacent to an upper surface and a side surface of the protruding semiconductor layer via a first insulating film including a charge accumulation film and extending in a second direction crossing the first direction;

a control gate electrode adjacent to the memory gate electrode via the first insulating film, adjacent to the upper surface and the side surface of the protruding semiconductor layer via a second insulating film, and extending in the second direction; and

a source region and a drain region sandwiching the memory gate electrode and the control gate electrode therebetween in the first direction of the protruding semiconductor layer,

wherein the memory gate electrode has

     1) a first gate electrode adjacent to a side surface of the protruding semiconductor layer via the first insulating film and in contact with the insulating film positioned on the side surface of the protruding semiconductor layer and

     2) a second gate electrode adjacent to the upper surface of the protruding semiconductor layer via the first insulating film and in contact with the insulating film positioned on the upper surface of the protruding semiconductor layer,

wherein the first gate electrode and the second gate electrode include respectively different electrode materials,

wherein a boundary surface between the first gate electrode and the second gate electrode lies on the side of the main surface with respect to the upper surface of the protruding semiconductor layer, and

wherein the electrode material of the second gate electrode has a work function higher than that of the electrode material of the first gate electrode.

10. The semiconductor device according to claim 9,

wherein the electrode material of the first gate electrode is polysilicon, and

wherein the electrode material of the second gate electrode is any of Al, Ti, Ta, Ru, W, and alloy materials containing any of Al, Ti, Ta, Ru, and W.

11. The semiconductor device according to claim 10, wherein the first gate electrode and the second gate electrode have therebetween a barrier metal.

12. The semiconductor device according to claim 9, wherein the electrode material of the first gate electrode is polysilicon, and

wherein the electrode material of the second gate electrode is a metal silicide.

13. The semiconductor device according to claim 12, wherein the first gate electrode and the second gate electrode have therebetween a silicon oxide film.

14. The semiconductor device according to claim 9, wherein the respective electrode materials of the first gate electrode and the second gate electrode are each any of Al, Ti, Ta, Ru, W, and alloy materials containing any of Al, Ti, Ta, Ru, and W.

15. The semiconductor device according to claim 10, wherein the first gate electrode and the second gate electrode have therebetween a work function control film including TaN or TiN.

16. The semiconductor device according to claim 15, wherein the first gate electrode and the work function control film and the second gate electrode and the work function control film each have therebetween a barrier metal.

17. A method of manufacturing a semiconductor device, comprising the steps of:

(a) forming a fin over a main surface of a semiconductor substrate by photolithography;

(b) stacking a silicon oxide film, a silicon nitride film, and a silicon oxide film one after another and thereby forming a stacked film over the main surface of the semiconductor substrate to cover an upper surface and a side surface of the fin;

(c) after the step (b), forming a polysilicon film over the main surface of the semiconductor substrate;

(d) after the step (c), dry etching the semiconductor substrate to etch the polysilicon film until it comes below the upper surface of the fin; and

(e) after the step (d), forming a metal film over the main surface of the semiconductor substrate.

18. The method of manufacturing a semiconductor device according to claim 17, further comprising, between the step (a) and the step (b), the steps of:

(f) forming a polysilicon film over the main surface of the semiconductor substrate to cover the upper surface and the side surface of the fin; and

(g) after the step (f), processing the polysilicon film by photolithography into a control gate electrode.