Hierarchically elaborated phased-array antenna modules and method of operation

• US 10,439,284 B2
• Filed: 08/05/2013
• Issued: 10/08/2019
• Est. Priority Date: 01/28/2013
• Status: Active Grant

• Current Assignee: Tubis Technology Inc
• Original Assignee: Tubis Technology Inc
• Inventors: Wang, James, Chie, Chak
• Primary Examiner(s): Phan, Dao L
• Application Number:
  US13/959,542
• Publication Number:
  US 20140210667A1
• Time in Patent Office: 2,255 Days
• Field of Search: 342361, 342368, 342372, 342373, 375316, 375319
• CPC Class Codes: H01Q 1/2283 mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
• CPC Class Codes: H01Q 21/0025 Modular arrays
• CPC Class Codes: H01Q 21/061 Two dimensional planar arrays
• CPC Class Codes: H01Q 3/2605 Array of radiating elements provided with a feedback control over the element weights, e.g. adaptive arrays
• CPC Class Codes: H01Q 3/2629 Combination of a main antenna unit with an auxiliary antenna unit
• CPC Class Codes: H01Q 3/34 by electrical means active lenses or reflecting arrays H01Q3/46

Abstract

A phased-array antenna panel has front end modules mounted on a Printed Circuit Board (PCB). Several phased-array processing die, transform phase and gain according to a register array in an RFIC on the PCB. The register array are grouped into a local register group and a global register group. Each set of local registers control an individual antenna element and a global register group controls overall RFIC function. The apparatus elaborates phase shift weights into a submodule of a phased-array antenna system. Each submodule determines its own base phase shift weight per its unique location and configuration to accelerate antenna beam direction changes.

Claims

1. A submodule apparatus of an antenna array comprising:

a configuration store readable by a digital phase shift weight multiplier (multiplier);

said multiplier coupled to the configuration store;

a plurality of phase shifter circuits coupled to said multiplier and further each coupled to an external antenna array element; and

an operand receiver coupled to said multiplier and further communicatively coupled to a central control;

wherein the configuration store comprises phase shift error correction bias for each element of the antenna array, whereby phase shift weights for the phase shifter circuits determined by the multiplier operating on received operands are corrected by phase shift error bias stored in the configuration store.

2. A phased-array antenna panel comprising:

a plurality of front end modules, Ball Grid Array(BGA)-mounted to a main PANEL Printed Circuit Board (PCB);

the main PANEL PCB;

each front end module comprising;

a plurality of antenna elements;

the antenna element coupled to a frontend die;

the frontend die (submodule) coupled to a phased-array processing die;

wherein the antenna elements are embedded in the top of a substrate and the frontend dies and the phased-array processing die are flip-chip mounted onto the bottom layer of substrate of each front end module whereby input or output signals are conducted through the substrate to the phased-array processing die and to passive combiners and splitters embedded in the PANEL PCB; and

a transceiver die flip-chip mounted on the PANEL PCB whereby the antenna transmitted and received signals are frequency translated;

wherein, each submodule comprises;

a configuration store readable by a digital phase shift weight multiplier (multiplier);

said multiplier coupled to the configuration store;

a plurality of phase shifter circuits coupled to said multiplier and further coupled to an external antenna array element; and

an operand receiver coupled to said multiplier and further communicatively coupled to a central control;

wherein the configuration store comprises phase shift error correction bias for each element of the antenna array, whereby phase shift weights for the phase shifter circuits determined by the multiplier operating on received operands are corrected by phase shift error bias stored in the configuration store.

3. The phased-array antenna panel of claim 2 wherein said phased-array processing die comprising:

a single bus coupling

phased-array processing blocks (blocks);

said block comprising phase-shifters, combiners, splitters, gain equalizers, buffer amplifiers, and a digital signal control and interface circuit;

at least one global/individual indicator pad; and

a plurality of individual die address setting pads, said pads in combination enabling a first die address to be configured at a first location on a main PANEL Printed Circuit Board (PCB) which connects a plurality of die address pads to a first combination of logic high or logic low and a second die address to be configured at a second location on the PCB which connects a plurality of die address pads to a second combination of logic high or logic low whereby registers within each instantiated phased-array processing die are assigned unique addresses and whereby indexing is provided for use in a computational mode.

4. The PANEL printed circuit board (PCB) of claim 2 further comprising:

a data and address bus;

a plurality of die address pads and a global die selection pat and a transfer format mode pad, whereby a plurality of die address pads at a first location coupled to a first combination of logic high and logic low and a plurality of die address pads at a second location coupled to a second combination of logic high and logic low assigns unique addresses to registers within each instantiated phased-array processing die when coupled to pads at said locations.

5. The PANEL PCB of claim 4 further comprising:

at least one driver to buffer bus outputs;

the driver coupling a microcontroller master device and coupling a plurality of slave devices on each phased-array processing die.

6. The phased-array processing die of claim 3 further comprising:

a plurality of Radio Frequency circuits (RF chains);

a register array in each phased-array processing die grouped into a local register group and a global register group, the local registers physically placed close in proximity to said RF chains which each correspond to an element of array antenna,

whereby each set of local registers control an individual antenna element and said global register controls overall phased-array processing die function;

wherein at least one local register is a common register coupled to input output circuits of the phased-array processing die and further coupled to other local registers to distribute data values for each of the antenna elements.

7. A phased-array processing die comprising:

a single serial bus, said serial bus communicatively coupling a common register to a plurality of local registers, said serial bus further coupled to die address settings of the device whereby a single pointer is disseminated to all antenna elements or whereby an indexing can be determined in a computation mode of operation;

a plurality of Radio Frequency circuits (RF chains);

a register array in each phased-array processing die grouped into a local register group and a global register group, the local registers physically placed close in proximity to said RF chains which each correspond to an element of array antenna,

whereby each set of local registers control an individual antenna element and said global register controls overall phased-array processing die function;

wherein at least one local register is a common register coupled to input output circuits of the phased-array processing die and further coupled to other local registers to distribute data values for each of the antenna elements;

a single bus coupling

phased-array processing blocks (blocks);

said block comprising phase-shifters, combiners, splitters, gain equalizers, buffer amplifiers, and a digital signal control and interface circuit;

at least one global/individual indicator pad; and

a plurality of individual die address setting pads, said pads in combination enabling a first die address to be configured at a first location on a main PANEL Printed Circuit Board (PCB) which connects a plurality of die address pads to a first combination of logic high or logic low and a second die address to be configured at a second location on the PCB which connects a plurality of die address pads to a second combination of logic high or logic low whereby registers within each instantiated phased-array processing die are assigned unique addresses and whereby indexing is provided for use in a computational mode.