Optical switch control method, and apparatus

• US 10,439,736 B2
• Filed: 12/18/2017
• Issued: 10/08/2019
• Est. Priority Date: 06/19/2015
• Status: Active Grant

• Current Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Original Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Inventors: Huang, Yongbing, Cao, Tongtong, Hao, Qinfen, Pan, Shuncheng
• Primary Examiner(s): Tsai, Henry
• Assistant Examiner(s): Daley, Christopher
• Application Number:
  US15/846,139
• Publication Number:
  US 20180109327A1
• Time in Patent Office: 659 Days
• CPC Class Codes: G06F 12/0833 in combination with broadcast means (e.g. for invalidation or updating)
• CPC Class Codes: G06F 15/80 comprising an array of processing units with common control, e.g. single instruction multiple data processors G06F15/82 takes precedence ; for correlation function computation G06F17/15
• CPC Class Codes: H04B 10/801 using optical interconnects, e.g. light coupled isolators, circuit board interconnections
• CPC Class Codes: H04Q 11/00 Selecting arrangements for multiplex systems multiplex systems H04J
• CPC Class Codes: H04Q 11/0062 Network aspects

Abstract

An optical switch control method and an apparatus are disclosed, to reduce impact on access performance by time overheads of optical link switching. The method includes: receiving an optical link establishment request sent by a computation node; determining whether the first optical link that needs to be established conflicts with the existing optical link; and if the first optical link that needs to be established conflicts with the existing optical link, determining whether to allow establishment of the first optical link, and establishing the first optical link if the establishment of the first optical link is allowed; or establishing the first optical link if the first optical link that needs to be established does not conflict with the existing optical link.

Claims

1. An optical switch control method, comprising:

receiving, by an optical switch chip, a first optical link establishment request sent by a computation node, wherein the first optical link establishment request carries an identifier of the computation node, an identifier of a first memory node to be accessed by the computation node, and first priority indication information of a first optical link to be established between the computation node and the first memory node;

determining, by the optical switch chip according to information about an existing optical link and the first priority indication information, the first optical link to be established conflicts with the existing optical link;

determining, by the optical switch chip, according to the first priority indication information, priority indication information of the existing optical link and link switching overheads of a first conflicting optical link, to allow establishment of the first optical link when the first optical link to be established conflicts with the existing optical link; and

establishing the first optical link when the establishment of the first optical link is allowed.

2. The method according to claim 1, wherein determining, by the optical switch chip, the first optical link to be established conflicts with the existing optical link comprises:

determining that the first optical link to be established and the existing optical link have a same optical fiber or port.

3. The method according to claim 1, wherein determining, by the optical switch chip according to the first priority indication information, priority indication information of the existing optical link and link switching overheads of a first conflicting optical link, to allow establishment of the first optical link comprises:

determining, by the optical switch chip, the link switching overheads of the first conflicting optical link are greater than a preset value;

determining, according to the first priority indication information and priority indication information of the first conflicting optical link, a priority of the first optical link is higher than a priority of the first conflicting optical link; and

allowing the establishment of the first optical link when the priority of the first optical link is higher than the priority of the first conflicting optical link.

4. The method according to claim 1, further comprising:

receiving, by the optical switch chip, a second optical link establishment request sent by the computation node, wherein the second optical link establishment request carries the identifier of the computation node, an identifier of a second memory node to be accessed by the computation node, and second priority indication information of a second optical link to be established between the computation node and the second memory node;

determining, by the optical switch chip according to information about the existing optical link and the second priority indication information, the second optical link to be established does not conflict with the existing optical link; and

establishing the second optical link when the second optical link to be established does not conflict with the existing optical link.

5. The method according to claim 1, further comprising:

receiving, by the optical switch chip, a third optical link establishment request sent by the computation node, wherein the third optical link establishment request carries the identifier of the computation node, an identifier of a third memory node to be accessed by the computation node, and third priority indication information of a third optical link to be established between the computation node and the third memory node;

determining, by the optical switch chip according to information about the existing optical link and the third priority indication information, the third optical link to be established conflicts with the existing optical link;

determining, by the optical switch chip according to the third priority indication information, priority indication information of the existing optical link and link switching overheads of a second conflicting optical link, not to allow establishment of the third optical link when the third optical link to be established conflicts with the existing optical link.

6. The method according to claim 5, wherein determining, by the optical switch chip according to the third priority indication information, priority indication information of the existing optical link and link switching overheads of a second conflicting optical link, not to allow establishment of the third optical link when the third optical link to be established conflicts with the existing optical link, comprises:

determining, by the optical switch chip, the link switching overheads of the second conflicting optical link are not greater than a preset value.

7. The method according to claim 5, wherein determining, by the optical switch chip according to the third priority indication information, priority indication information of the existing optical link and link switching overheads of a second conflicting optical link, not to allow establishment of the third optical link when the third optical link to be established conflicts with the existing optical link, comprises:

determining, by the optical switch chip according to the third priority indication information and priority indication information of the second conflicting optical link, a priority of the third optical link is not higher than a priority of the second conflicting optical link.

8. The method according to claim 1, wherein the link switching overheads of the first conflicting optical link are determined according to a link re-arrangement time, an optical receiver lock time, and a data link switching and recovery time.

9. An optical switch control method, applied to communication between a computation node and a memory node, wherein an optical link for communication is established between the computation node and the memory node by using an optical switch chip, and the method comprises:

receiving, by the computation node, a request for accessing a memory node in one or more time periods, and obtaining an identifier and an access feature of the memory node accessed in the one or more time periods, wherein the access feature comprises any one or a combination of multiple of a bandwidth of the accessed memory node, address distribution of the accessed memory node, a distribution status of access requests corresponding to different amounts of data, and a ratio of requests for reading data from the memory node to requests for writing data into the memory node;

searching, by the computation node, a phase feature library according to the identifier and the access feature of the memory node accessed in the one or more time periods, wherein the phase feature library stores an identifier and an access feature of each memory node to be accessed by the computation node in each time period in each processing phase;

determining, from the phase feature library, a processing phase to which a time period matching the identifier and the access feature of the memory node accessed in the one or more time periods belongs; and

obtaining an identifier and an access feature of each memory node to be accessed in a next time period of the matched time period in the determined processing phase;

determining, by the computation node according to a quantized value corresponding to the access feature of each memory node that needs to be accessed in the next time period, priority indication information of an optical link to be established between the computation node and each memory node to be accessed in the next time period;

generating, by the computation node, an optical link establishment request, and sending the optical link establishment request to the optical switch chip, wherein the optical link establishment request carries an identifier of the computation node and the identifier of each memory node that needs to be accessed in the next time period, and carries the priority indication information of the optical link that needs to be established in the next time period between the computation node and each memory node that needs to be accessed.

10. The method according to claim 9, wherein searching, by the computation node, a phase feature library according to the identifier and the access feature of the memory node accessed in the one or more time periods, and determining, from the phase feature library, a processing phase to which a time period matching the identifier and the access feature of the memory node accessed in the one or more time periods belongs comprises:

searching, by the computation node, data in a table of the phase feature library;

determining data that is in the table matches the identifier and the access feature of the memory node accessed in the one or more time periods; and

determining a processing phase corresponding to the matched data in the table.

11. An optical switch chip, comprising:

a processor; and

storage having a plurality of stored instructions that, when executed by the processor, cause the optical switch chip to;

receive, a first optical link establishment request sent by a computation node, wherein the first optical link establishment request carries an identifier of the computation node, an identifier of a first memory node to be accessed by the computation node, and first priority indication information of a first optical link to be established between the computation node and the first memory node,

determine, according to information about an existing optical link and the first priority indication information, the first optical link to be established conflicts with the existing optical link,

determine, according to the first priority indication information, priority indication information of the existing optical link and link switching overheads of a first conflicting optical link, to allow establishment of the first optical link when the first optical link to be established conflicts with the existing optical link, and

establish the first optical link when the establishment of the first optical link is allowed.

12. The optical switch chip according to claim 11, wherein the plurality of stored instructions, when executed by the processor, further cause the optical switch chip to:

determine that the first optical link to be established conflicts with the existing optical link when the first optical link to be established and the existing optical link have a same optical fiber or port.

13. The optical switch chip according to claim 11, wherein the plurality of stored instructions, when executed by the processor, further cause the optical switch chip to:

determine the link switching overheads of the first conflicting optical link are greater than a preset value;

determine, according to the first priority indication information and priority indication information of the first conflicting optical link, a priority of the first optical link is higher than a priority of the first conflicting optical link;

allow the establishment of the first optical link when the priority of the first optical link is higher than the priority of the first conflicting optical link.

14. The optical switch chip according to claim 11, wherein the plurality of stored instructions, when executed by the processor, further cause the optical switch chip to:

receive, a second optical link establishment request sent by the computation node, wherein the second optical link establishment request carries the identifier of the computation node, an identifier of a second memory node to be accessed by the computation node, and second priority indication information of a second optical link to be established between the computation node and the second memory node;

determine, according to information about the existing optical link and the second priority indication information, the second optical link to be established does not conflict with the existing optical link;

establish the second optical link when the second optical link to be established does not conflict with the existing optical link.

15. The optical switch chip according to claim 11, wherein the plurality of stored instructions, when executed by the processor, further cause the optical switch chip to:

receive, by an optical switch chip, a third optical link establishment request sent by the computation node, wherein the third optical link establishment request carries the identifier of the computation node, an identifier of a third memory node to be accessed by the computation node, and third priority indication information of a third optical link to be established between the computation node and the third memory node;

determine, according to information about the existing optical link and the third priority indication information, the third optical link to be established conflicts with the existing optical link;

determine, according to the third priority indication information, priority indication information of the existing optical link, and link switching overheads of a second conflicting optical link, not to allow establishment of the third optical link when the third optical link to be established conflicts with the existing optical link.

16. The optical switch chip according to claim 15, wherein the plurality of stored instructions, when executed by the processor, further cause the optical switch chip to:

determine not to allow establishment of the third optical link when the link switching overheads of the second conflicting optical link are not greater than a preset value.

17. The optical switch chip according to claim 15, wherein the plurality of stored instructions, when executed by the processor, further cause the optical switch chip to:

determine not to allow establishment of the third optical link when a priority of the third optical link is not higher than a priority of the second conflicting optical link.

18. The optical switch chip according to claim 11, wherein the link switching overheads of the first conflicting optical link are determined according to a link re-arrangement time, an optical receiver lock time, and a data link switching and recovery time.