Communication channel calibration using feedback

• US 10,439,740 B2
• Filed: 07/17/2017
• Issued: 10/08/2019
• Est. Priority Date: 06/09/2004
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Kim, Jun, Richardson, Wayne S., Chiu, Glenn
• Primary Examiner(s): Raymond, Edward
• Application Number:
  US15/652,047
• Publication Number:
  US 20180006737A1
• Time in Patent Office: 813 Days
• Field of Search: 702 69, 702 64- 67, 702182-185, 702188
• CPC Class Codes: H04B 17/11 for calibration
• CPC Class Codes: H04L 2025/03802 Signalling on the reverse channel
• CPC Class Codes: H04L 25/03343 Arrangements at the transmitter end
• CPC Class Codes: H04L 5/1438 Negotiation of transmission parameters prior to communication modified according to link quality H04L1/0001

Abstract

A method for calibrating a communication channel coupling first and second components includes transmitting a data signal from the first component to the second component on the communication channel, and sensing a characteristic, such as phase, of the data signal on the second component. Information about the sensed characteristic is fed back to the first component using an auxiliary channel. An adjustable parameter, such as phase, for the transmitter is adjusted on the first component in response to the information. Also, a characteristic of a data signal received from the transmitter on the second component is sensed and used to adjust an adjustable parameter for the receiver on the first component.

Claims

1. An integrated circuit (IC) memory chip, comprising:

memory core circuitry;

interface circuitry coupled to the memory core circuitry, the interface circuitry including multiple input/output (I/O) ports for coupling to respective data links; and

calibration circuitry including

sensor circuitry to detect signal parameter information at each of the I/O ports, the signal parameter information associated with data received at the I/O ports; and

a sideband I/O port for coupling to a sideband channel, the sideband port to communicate the signal parameter information via the sideband channel to a memory controller.

2. The IC memory chip of claim 1, wherein the memory core circuitry includes dynamic random access memory (DRAM) storage cells.

3. The IC memory chip of claim 1, wherein the multiple I/O ports operate at a first data rate, and the sideband I/O port operates at a second data rate that is less than the first data rate.

4. The IC memory chip of claim 1, wherein the sideband I/O port includes a wired link transmitter.

5. The IC memory chip of claim 4, wherein the sideband I/O port operates in a first mode to communicate the signal parameter information to the memory controller, and in a second mode to communicate second information other than the signal parameter information with the memory controller, the second information from the group comprised of control information, test information, and system management information.

6. The IC memory chip of claim 1, wherein the sideband I/O port includes a wireless transmitter.

7. The IC memory chip of claim 1, wherein the sensor circuitry comprises multiple phase detectors, each of the multiple phase detectors coupled to a respective I/O port to detect phase information of data received at the respective I/O port.

8. The IC memory chip of claim 7, wherein the signal parameter information comprises phase information of data signals relative to a reference clock signal.

9. The IC memory chip of claim 1, further comprising:

logic to accumulate the signal parameter information and to compose a communication packet for transmission to the memory controller, the communication packet including the signal parameter information.

10. A method of operation in an integrated circuit (IC) memory device, the method comprising:

receiving data signals along multiple data links from a memory controller;

generating sensed information associated with the data signals of the multiple data links by

sensing signal parameter information associated with the data signals;

composing the sensed information associated with the data signals of the multiple data links into calibration information; and

transmitting the calibration information to the memory controller via a sideband port.

11. The method of claim 10, wherein generating sensed information comprises generating phase information associated with the data signals relative to a reference clock, the method further comprising:

receiving subsequent data signals having adjusted phase parameters, the adjusted phase parameters based on the calibration information transmitted to the memory controller.

12. The method of claim 10, wherein generating sensed information comprises generating equalization characteristics of the data signals, the method further comprising:

receiving subsequent data signals having adjusted equalization parameters, the adjusted equalization parameters based on the calibration information transmitted to the memory controller.

13. The method of claim 10, wherein the sensed information comprises generating amplitude information associated with the data signals, the method further comprising:

receiving subsequent data signals having adjusted amplitude parameters, the adjusted amplitude parameters based on the calibration information transmitted to the memory controller.

14. The method of claim 10, wherein the transmitting comprises dispatching a communication packet including the sensed information.

15. The method of claim 10, wherein the data signals are received at a first data rate, and wherein the transmitting is carried out at a second data rate that is less than the first data rate.

16. The method of claim 10, further comprising:

sharing the sideband port for communicating second information between the IC memory device and the memory controller, the second information other than the signal parameter information and from the group comprised of control information, test information, and system management information.

17. An integrated circuit (IC) DRAM memory chip comprising:

receiver circuitry for coupling to multiple data links, the receiver circuitry to receive data signals from a memory controller;

sensing circuitry to generate sensed information associated with the data signals of the multiple data links by sensing signal parameter information associated with the data signals;

logic to accumulate the sensed information associated with the data signals of the multiple data links into calibration information; and

transmitter circuitry to transmit the calibration information to the memory controller via a sideband port.

18. The IC DRAM memory chip according to claim 17, wherein the sensing circuitry comprises phase detector circuitry.

19. The IC DRAM memory chip according to claim 18, wherein the signal parameter information comprises phase information of the data signals relative to a reference clock signal.

20. The IC DRAM memory chip according to claim 17, wherein the sideband I/O port operates in a first mode to communicate the signal parameter information to the memory controller, and in a second mode to communicate second information other than the signal parameter information with the memory controller, the second information from the group comprised of control information, test information, and system management information.