Memory page request for optimizing memory page latency associated with network nodes

• US 10,439,960 B1
• Filed: 11/15/2016
• Issued: 10/08/2019
• Est. Priority Date: 11/15/2016
• Status: Active Grant

• Current Assignee: Ampere Computing LLC
• Original Assignee: Ampere Computing LLC
• Inventors: Jindal, Ankit, Sawargaonkar, Pranavkumar, Chudgar, Keyur
• Primary Examiner(s): Tokuta, Shean
• Application Number:
  US15/351,477
• Time in Patent Office: 1,057 Days
• CPC Class Codes: G06F 12/0692 Multiconfiguration, e.g. local and global addressing
• CPC Class Codes: G06F 2009/45583 Memory management, e.g. access or allocation
• CPC Class Codes: G06F 2212/1008 Correctness of operation, e.g. memory ordering
• CPC Class Codes: G06F 9/45533 Hypervisors; Virtual machine monitors
• CPC Class Codes: G06F 9/45558 Hypervisor-specific management and integration aspects
• CPC Class Codes: H04L 49/103 using a shared central buffer; using a shared memory
• CPC Class Codes: H04L 49/109 Integrated on microchip, e.g. switch-on-chip
• CPC Class Codes: H04L 49/15 Interconnection of switching modules

Abstract

Various aspects optimize memory page latency and minimize inter processor interrupts associated with network nodes in a virtual computer system. For example, a system can include a first network node and a second network node. The first network node generates a memory page request in response to an invalid memory access associated with a virtual central processing unit of the first network node. The memory page request includes an identifier for the virtual central processing unit. The second network node receives the memory page request and provides memory data associated with memory page request to the first network node.

Claims

1. A system for optimizing memory page latency associated with network nodes, comprising:

a first network node configured for generating a memory page request in response to an invalid memory access associated with a first virtual central processing unit of a plurality of virtual central processing units of the first network node, the memory page request comprising an identifier for the first virtual central processing unit; and

a second network node configured for receiving the memory page request and providing memory data associated with memory page request to the first network node,

wherein the first network node is configured for allocating a physical address space associated with the first network node in response to the invalid memory access;

wherein the first network node is configure for mapping a guest physical address associated with the invalid memory access to a physical address associated with the physical address space, and

wherein the second network node is configured for transmitting a memory page acknowledgment to the first network node, and the memory page acknowledgement transmitted from the second network node to the first network node comprises the identifier for the first virtual central processing unit.

2. The system of claim 1, wherein the memory page request further comprises the guest physical address associated with the invalid memory access.

3. The system of claim 1, wherein the memory page request further comprises the physical address associated with the physical address space.

4. The system of claim 1, wherein the first network node is configured for generating an interrupt signal for exclusively interrupting a first host central processing unit associated with the first virtual central processing unit identified in the memory page acknowledgment, wherein the first host central processing unit is one of a plurality of host central processing units of the first network node, each host central processing units associated with one or more of the plurality of virtual central processing units of the first network node.

5. The system of claim 4, wherein the first network node is configured for generating the interrupt signal for the first host central processing unit without broadcasting the interrupt signal to other host central processing units of the plurality of host central processing units of the first network node.

6. The system of claim 1, wherein the memory data is provided to an operating system of the first network node by a first host central processing unit associated with the first virtual central processing unit identified in the memory page acknowledgment.

7. The system of claim 1, wherein the first network node is a first system on a chip (SoC) and the second network node is a second SoC different from the first SoC.

8. A method for optimizing memory page latency associated with network nodes, comprising:

generating a memory page request that comprises an identifier for a first virtual central processing unit of a plurality of virtual central processing units of a first network node in response to an invalid memory access associated with the first virtual central processing unit;

transmitting the memory page request from the first network node to a second network node;

receiving, at the first network node from the second network node, a memory page acknowledgment that comprises the identifier for the first virtual central processing unit; and

exclusively interrupting a first host central processing unit associated with the first virtual central processing unit that corresponds to the identifier in the memory page acknowledgment, wherein the first host central processing unit is one of a plurality of host central processing units of the first network node, each host central processing units associated with one or more of the plurality of virtual central processing units of the first network node.

9. The method of claim 8, further comprising mapping, by the first network node, a guest physical address to a host physical address.

10. The method of claim 8, further comprising halt processing, by the first virtual central processing unit, in response to the invalid memory access.

11. The method of claim 10, further comprising employing a hypervisor associated with the first host central processing unit to notify the first virtual central processing unit to resume processing in response to the memory page acknowledgment.

12. The method of claim 8, further comprising receiving memory data associated with the memory page request.

13. The method of claim 8, further comprising receiving memory data from a memory location that corresponds to a guest physical address associated with the invalid memory access.

14. A network device, comprising:

a first virtual central processing unit of a plurality of virtual central processing units, the first virtual central processing unit configured for generating an abort signal in response to an invalid memory access associated with a guest physical address;

a memory coherency manager configured for generating a page request message in response to the invalid memory access, the page request message comprising an identifier for the first virtual central processing unit, and the page request message being configured for being transmitted, by the network device, to another network device coupled to the network device via a physical communication channel; and

a first host central processing unit associated the first virtual central processing unit and configured for to be exclusively interrupted in response to receipt, by the network device, of a memory page acknowledgement, from the another network device, wherein the memory page acknowledgement comprises the identifier for the first virtual central processing unit.

15. The network device of claim 14, wherein the memory coherency manager is configured for allocating a physical address space for the physical address in a memory of the network device and mapping of the guest physical address to a physical address associated with the network device.

16. The network device of claim 15, wherein the first host central processing unit is farther configured for restoring functionality of the first virtual central processing unit in response to the mapping.

17. The network device of claim 14, wherein the network device is a first system on a chip (SoC).

18. The network device of claim 17, wherein the another network device is a second SoC different from the first SoC.

19. The network device of claim 18, wherein the first SoC and the second SoC are associated with the same physical device.