Vertical sense devices in vertical trench MOSFET

• US 10,444,262 B2
• Filed: 06/27/2017
• Issued: 10/15/2019
• Est. Priority Date: 08/19/2014
• Status: Active Grant

• Current Assignee: Vishay Siliconix
• Original Assignee: Vishay Siliconix
• Inventors: Shibib, M. Ayman, Zhang, Wenjie
• Primary Examiner(s): Abdelaziez, Yasser A
• Application Number:
  US15/634,901
• Publication Number:
  US 20170322239A1
• Time in Patent Office: Days
• CPC Class Codes: G01R 19/0092 measuring current only all subgroups of G01R19/00 take precedence
• CPC Class Codes: G01R 19/15 Indicating the presence of current
• CPC Class Codes: H01L 21/02129 the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/28035 the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities H01L21/28105 takes precedence
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/308 using masks H01L21/3063, H01L21/3065 take precedence
• CPC Class Codes: H01L 21/32133 by chemical means only
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/0727 in combination with diodes, or capacitors or resistors
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7815 : with voltage or current sensing structure, e.g. emulator section, overcurrent sensing cell

Abstract

Vertical sense devices in vertical trench MOSFET. In accordance with an embodiment of the present invention, a semiconductor device includes a main vertical trench metal oxide semiconductor field effect transistor (main-MOSFET). The main-MOSFET includes a plurality of parallel main trenches, wherein the main trenches comprise a first electrode coupled to a gate of the main-MOSFET, and a plurality of main mesas between the main trenches, wherein the main mesas comprise a main source and a main body of the main-MOSFET. The semiconductor device also includes a sense-diode. The sense-diode includes a plurality of sense-diode trenches, wherein each of the sense-diode trenches comprises a portion of one of the main trenches, and a plurality of sense-diode mesas between the source-FET trenches, wherein the sense-diode mesas comprise a sense-diode anode that is electrically isolated from the main source of the main-MOSFET.

Claims

1. A semiconductor device comprising:

a main vertical trench metal oxide semiconductor field effect transistor (main-MOSFET) comprising;

a plurality of parallel main trenches, wherein said main trenches comprise a first electrode coupled to a gate of said main-MOSFET; and

a plurality of main mesas between said main trenches, wherein said main mesas comprise a main source and a main body of said main-MOSFET; and

a sense-diode comprising;

a plurality of sense-diode trenches, wherein each of said sense-diode trenches comprises a portion of one of said main trenches; and

a plurality of sense-diode mesas between said source-FET trenches, wherein said sense-diode mesas comprise a sense-diode anode that is electrically isolated from said main source of said main-MOSFET.

2. The semiconductor device of claim 1 wherein said main FET trenches comprise a first electrode coupled to said gate of said main-MOSFET and a second electrode electrically isolated from said main gate electrode.

3. The semiconductor device of claim 1 wherein portions of said main MOSFET surrounds said sense-diode on at least three sides.

4. The semiconductor device of claim 1 further comprising a surface isolation region free of surface metallization between said sense-diode and said main MOSFET on said at least three sides.

5. The semiconductor device of claim 4 wherein portions of said surface isolation region are formed between isolation trenches crossing said parallel main trenches.

6. The semiconductor device of claim 1 further comprising:

at least two first isolation trenches crossing said parallel main trenches.

7. The semiconductor device of claim 6 further comprising:

a plurality of second isolation trenches, formed outside of an active area of said sense-diode, wherein each of said second isolation trenches comprises a portion of one of said main trenches.

8. A semiconductor device comprising:

a vertical trench main MOSFET (main-FET) configured to control a drain source current;

a vertical trench sense-diode (sense-diode) configured to produce a signal corresponding to a temperature of said main-FET; and

an isolation trench configured to isolate said main-FET from said sense-diode,

wherein said isolation trench is formed at an angle to, and intersects a plurality of trenches of said main-FET.

9. The semiconductor device of claim 8 wherein vertical trenches of said main-FET comprise at least two vertically aligned electrodes, electrically insulated from one another.

10. The semiconductor device of claim 9 wherein a lower of said electrodes is coupled to a source of said main-FET.

11. The semiconductor device of claim 9 wherein an upper of said electrodes is coupled to a gate of said main-FET.

12. The semiconductor device of claim 9 wherein said angle is greater than 40 degrees.

13. The semiconductor device of claim 9 wherein said angle is substantially 90 degrees.

14. The semiconductor device of claim 9 wherein a cathode of said sense-diode and a drain terminal of said main-FET are electrically coupled.

15. A semiconductor device comprising:

a main-FET comprising a main-FET source region;

a sense-diode configured to produce a signal corresponding to a temperature of said main-FET, said sense-diode comprising;

a plurality of first trenches formed in a first horizontal dimension configured to isolate a sense-diode anode region from said main-FET source region,

wherein each of said trenches comprises multiple alternating layers of conductors and dielectrics in a vertical dimension; and

at least one second trench in a perpendicular horizontal dimension located between said sense-diode anode region and said main-FET source region and configured to isolate said sense-diode anode region from said main-FET source region; and

a buffer region separating said sense-diode anode region and said main-FET source region.

16. The semiconductor device of claim 15 wherein trenches of said main FET comprise a first electrode coupled to a gate electrode of said main-MOSFET and a second electrode electrically isolated from said gate electrode.

17. The semiconductor device of claim 15 further comprising a surface isolation region free of surface metallization between said sense-diode and said main MOSFET on said at least three sides of said sense-diode.

18. The semiconductor device of claim 15 wherein electrodes within trenches of said sense-diode are electrically isolated from electrodes within trenches of said main-FET.

19. The semiconductor device of claim 15 wherein first and second electrodes within trenches of said sense-diode are electrically coupled to the anode terminal of said sense-diode.