Computing device executing program performing method of analyzing power noise in semiconductor device, semiconductor device design method, and program storage medium storing program

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First Claim
1. A method of generating a semiconductor device design in a computing device, the method comprising:
 designing a power network for a semiconductor device and a plurality of cells connected to the power network to obtain a generated semiconductor device design;
analyzing power noise of the power network based on modeling the semiconductor device as a power network model and a transistor model,generating a generated semiconductor device design as a result of analyzing the power noise of the power network based on first modified current information and second modified current information, wherein the first modified current information is generated at a first time as a result of a first analysis based on an assumption that the power network model exists, and the second modified current information is generated at a second time after the first time by modifying present current information based on an ideal supply voltage condition using the result of the first analysis; and
storing at least part of the generated semiconductor device design in a memory associated with the computing device.
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Abstract
A method of analyzing power noise in a semiconductor device includes; generating modified current information by modifying present current information based on a previous analysis result, updating a current vector based on the modified current information, and generating a present analysis result by calculating a voltage vector from the updated current vector.
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20 Claims
 1. A method of generating a semiconductor device design in a computing device, the method comprising:
designing a power network for a semiconductor device and a plurality of cells connected to the power network to obtain a generated semiconductor device design; analyzing power noise of the power network based on modeling the semiconductor device as a power network model and a transistor model, generating a generated semiconductor device design as a result of analyzing the power noise of the power network based on first modified current information and second modified current information, wherein the first modified current information is generated at a first time as a result of a first analysis based on an assumption that the power network model exists, and the second modified current information is generated at a second time after the first time by modifying present current information based on an ideal supply voltage condition using the result of the first analysis; and storing at least part of the generated semiconductor device design in a memory associated with the computing device.  View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
 11. A method of generating a semiconductor device design in a computing device, the method comprising:
designing a power network for a semiconductor device and a plurality of cells connected to the power network to obtain a generated semiconductor device design; analyzing power noise of the power network based on modeling the semiconductor device as a power network model and a transistor model; generating a generated semiconductor device design as a result of analyzing power noise of the power network to generate a result of analyzing the power noise of the power network based on modeling the semiconductor device as a power network model and a transistor model and based on first modified current information and second modified current information, wherein the first modified current information is generated at a first time as a result of a first analysis by modifying first present current information based on an ideal supply voltage condition using the result of a previous analysis of the power noise of the power network, and the second modified current information is generated at a second time after the first time as a result of a second analysis by modifying second present current information based on an ideal supply voltage condition using the result of the first analysis; and storing at least part of the generated semiconductor device design in a memory associated with the computing device.  View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
 20. A method of generating a semiconductor device design in a computing device, the method comprising:
designing a power network for a semiconductor device and a plurality of cells connected to the power network to obtain a generated semiconductor device design; analyzing power noise of the power network based on modeling the semiconductor device as a power network model and a transistor model; generating a generated semiconductor device design as a result of analyzing power noise of the power network to generate a result of analyzing the power noise of the power network based on modeling the semiconductor device as a power network model and a transistor model and based on first modified current information, second modified current information and third modified current information, wherein the first modified current information is generated at a first time as a result of a first analysis by modifying first present current information based on an assumption that the power network model exists, the second modified current information is generated at a second time after the first time as a result of a second analysis by modifying second present current information based on an ideal supply voltage condition using the result of the first analysis of the power noise of the power network, and the third modified current information is generated at a third time after the second time as a result of a third analysis by modifying third present current information based on an ideal supply voltage condition using the result of the second analysis; and storing at least part of the generated semiconductor device design in a memory associated with the computing device.
1 Specification
This is a Divisional of U.S. application Ser. No. 14/949,178, filed Dec. 4, 2015, which claims the benefit of Korean Patent Application No. 1020140174202 filed on Dec. 5, 2014, the subject matter of which is hereby incorporated by reference.
Embodiments of the inventive concept relate generally to computing devices capable of executing a program performing a method that analyzes power noise in a semiconductor device. Other embodiments of the inventive concept relate to methods of providing semiconductor device designs having more accurate power noise characterization, as well as program storage media storing program(s) performing such methods.
Contemporary semiconductor devices include a vast number of semiconductor elements that respectively and/or collectively operate in prescribed manner(s) in response to one or more applied operating voltages. Thus, the design, characterization, generation and application of various operating voltages and power voltages are important consideration in the overall design and operation of a semiconductor device. Power voltage(s) are applied to various power supply terminal(s) of a semiconductor device. These power supply voltages may then be connect to respective semiconductor elements, or groups of semiconductor elements, via a socalled power network. In like manner, various operating voltages derived from one or more power voltages may be distributed via some or all the power network. As a result, the power network constitutes a complicated power transmission path.
However, the power network (or power transmission path taken as a whole or in various portions) may be understood as having an electrical resistance. Hence, an externally provided power voltage is not directly applied to the various semiconductor elements, but is instead indirectly coupled to the semiconductor elements via a power network component having a resistance value. As a result, some nonzero drop in an applied power voltage will occur as the result of being connected to the semiconductor elements via the power network. Under certain operating conditions, it is possible that a power voltage applied to semiconductor elements may drop to the point where normal operation of the semiconductor device is not ensured. Hereafter, a dropped voltage resulting from the foregoing phenomenon will be referred to as ‘power noise’. Given the narrowing margins and decreasing amplitudes of power voltages and operating voltages variously applied in contemporary semiconductor devices, it is increasingly important to accurately model or analyze power noise during the design of a semiconductor device.
According to an aspect of the inventive concept, there is provided a computing device capable of executing a program performing a method of analyzing power noise in a semiconductor device which is to be modeled as a power network model and a transistor model, the method including generating a first analysis result at a first point of time by performing an arithmetic operation on first modified current information and a power network matrix, wherein the first modified current information is generated based on an assumption that the power network model exists; generating a second analysis result at a second point of time, wherein the second analysis result is second modified current information obtained by modifying second present current information, which is generated based on an ideal supply voltage condition, by using the first analysis result; and generating a power noise analysis result by performing an arithmetic operation on the second analysis result and the power network matrix.
In some embodiments, the method may further include generating the power network matrix based power network information.
In some embodiments, the second modified current information may be generated by performing an arithmetic operation on the second present current information, the first analysis result, and parameters of the transistor model.
In some embodiments, an equation for calculating the second modified current information may be derived from a rate between the second modified current information and the second present current information when the transistor model is present in a saturation region.
In some embodiments, the first analysis result and the power noise analysis result may be voltage vectors of nodes connected to the transistor model and the power network model.
In some embodiments, the previous analysis result may be a result of reflecting power noise when the power network model is connected the transistor model.
In some embodiments, the voltage vectors may be calculated using a linear analysis.
According to another aspect of the inventive concept, a method of designing a semiconductor device includes designing a power network of a semiconductor device and a plurality of cells connected to the power network; analyzing power noise in the semiconductor device by modeling the semiconductor device as a power network model and a transistor model and generating a power noise analysis result based on first modified current information and second modified current information, wherein the first modified current information is generated at a first point of time, based on an assumption that the power network model exists, and the second modified current information is obtained by modifying second present current information, which is generated at a second point of time based on an ideal supply voltage condition, by using the first analysis result; and modifying the semiconductor device based on the analyzed power noise.
In some embodiments, the analyzing of the power noise in the semiconductor device may include generating the first analysis result at a first point of time by performing an arithmetic operation on the first modified current information and a power network matrix; generating a second analysis result at a second point of time, wherein the second analysis result is the second modified current information obtained by modifying the second present current information by using the first analysis result; and generating the power noise analysis result at the second point of time by performing an arithmetic operation on the second analysis result and the power network matrix.
In some embodiments, the analyzing of the power noise in the semiconductor device may further include generating the power network matrix based on power network information.
In some embodiments, the second modified current information may be generated by performing an arithmetic operation on the second present current information, the first analysis result, and parameters of the transistor model.
In some embodiments, an equation for calculating the second modified current information may be derived from a rate between the second modified current information and the second present current information when the transistor model is present in a saturation region.
In some embodiments, the first analysis result and the power noise analysis result may be voltage vectors of nodes connected to the transistor model and the power network model.
In some embodiments, the first analysis result may be a result of reflecting power noise when the power network model is connected the transistor model.
In some embodiments, the power noise analysis result may be calculated using a linear analysis.
According to another aspect of the inventive concept, there is provided a program storage medium storing a computer program causing a computer to perform a method of analyzing power noise in a semiconductor device which is to be modeled as a power network model and a transistor model, the method including generating a first analysis result at a first point of time by performing an arithmetic operation on first modified current information and a power network matrix, wherein the first modified current information is generated based on an assumption that the power network model exists; generating a second analysis result at a second point of time, wherein the second analysis result is second modified current information obtained by modifying second present current information, which is generated based on an ideal supply voltage condition, by using the first analysis result; and generating a power noise analysis result by performing an arithmetic operation on the second analysis result and the power network matrix.
The inventive concept may be more readily understood from a consideration of the written description that follows taken in conjunction with the accompanying drawings in which:
The inventive concept now will be described in some additional detail with reference to the accompanying drawings. The inventive concept may, however, be embodied in many different forms and should not be construed as being limited to only the illustrated embodiments Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Throughout the written description and drawings, like reference numbers and labels are used to denote like or similar elements, features or steps.
It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items and may be abbreviated as “/”.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first signal could be termed a second signal, and, similarly, a second signal could be termed a first signal without departing from the teachings of the disclosure.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” or “includes” and/or “including” when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present application, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Power noise analysis is a method of analyzing power noise generated in a power network when a semiconductor device operates. In one particular approach to power noise analysis, a linear circuit equation is defined by converting the power network of a given semiconductor device into an equivalent RC (resistorcapacitor) circuit. Once this modeling conversion is made, the value of a current passing through an active element (e.g., a MetalOxide Semiconductor Field Effect Transistor—MOSFET) connected to the power network may be considered. That is, the MOSFET current may be considered as a current source and the resulting current may be calculated according to a linear analysis method, so as to analyze the power noise generated by the power network.
Here, the accuracy of a power analysis in relation to real life operating results will vary according to the accuracy and appropriateness of modeling assumptions and analysis tools. For example, in the context of the foregoing example, the accuracy of modeling the current passing through the MOSFET is quite important.
Referring to
The CPU 50 may be used to control the overall operation of the computer 10, as well the execution of one or more programs, stored wholly or in part on the computing system 10 and operating on the computing device 10. The particular focus of certain embodiments described herein is a specialty program hereafter referred to as a device design program 100.
The memory 80 may be used to store program information (e.g., programming code), program data, as well as final or intermediate data output by the execution of the device design program 100. In particular, the memory 80 may be used to store some or all of the device design program 100.
In the illustrated examples of
The design unit 110 may be used design one or more aspects of the semiconductor device 300 illustrated in part by
As illustrated in
In this context, power noise may be analyzed using the power noise analysis unit 120.
Each of the plurality of cells 320 may operate as a functional block of the semiconductor device 300, e.g., a sense amplifier of a semiconductor memory device, independently or in combination with at least one among the other cells 320. Only one of the many cells 320 is illustrated in
Although only one of the plurality of cells 320 is illustrated for convenience of explanation, the semiconductor device 300 may include several hundreds of thousands of cells 320 or more. Each of these cells 320 may be connected to a point (e.g., an intersection point of two or more lines or along a midpoint on a particular line) on the power network 310.
With the semiconductor device 300 in mind, the design unit 110 of
In
A resistance value of the power network model Rpn may vary according to the location of the cell 320 within a matrix of cells and/or according to position along one or more lines.
The transistor model MM is an equivalent transistor modeled after each of the plurality of cells 320. In some embodiments, the transistor model MM may be expressed as a NMOS transistor or a combination of a PMOS transistor and an NMOS transistor. However, for convenience of explanation, it is assumed in the working example of
For example, the transistor model MM may be one equivalent transistor modeled after a complicated circuit that includes the transistors M1 and M2 of the cell 320 of
A gate voltage Vg may be applied to a gate of the transistor model MM and drain current I will flow between a source and a drain of the transistor model MM. A source voltage Vs of the transistor model MM, i.e., a voltage of the first node N1, may be defined as a dropped voltage V.
The transistor model MM may have transistor parameters (e.g., a capacitance Cox per unit area of a channel, a ratio W/L between the width and the length of the channel, a lowfield mobility μ_{0}, θ(10−7/Tox), a threshold voltage Vth, etc., where the variable ‘Tox’ denotes the thickness of a gate oxide.
Accordingly, the design unit 110 of
In this context, the drain current I of the present current information CI is drain current I in a state in which it is assumed that the power network model Rpn does not exist in the semiconductor device model 400 of
The power noise analysis unit 120 may generate an analysis result AR obtained by analyzing power noise in the semiconductor device 300 based on the present current information CI, the power network information PNI, and the parameter information PI.
One exemplary approach to power noise analysis makes the following assumptions. First, it is assumed that the drain current I of the transistor model MM is current when the transistor model MM is present in a saturation region. This is because the transistor model MM is present in a triode region for a very short time and the saturation region is a significant region in terms of power consumption.
Second, it is assumed that the gate voltage Vg of the transistor model MM is the ground voltage VSS and the transistor model MM is in a ON state. Also, it is assumed that the source voltage Vs of transistor model MM is the power voltage VDD.
Third, it is assumed that the threshold voltage Vth of the transistor model MM is maintained constant.
Based on the foregoing assumptions, the power noise analysis unit 120 may calculate a voltage of the first node N1 with respect to power noise. Power noise in the semiconductor device 300 may change according to various operations of the semiconductor device 300 (e.g., a read operation, a write operation, etc.), and may even change with time during a single operation. Thus, the power noise analysis unit 120 may analyze power noise across a number of points in time (e.g., points t_{0 }to t_{n }in
Since the information PI, PNI, and CI correspond to each of the plurality of cells 320, a set of drain currents I may be expressed as a current vector I and a set of dropped voltages V may be expressed as a voltage vector V.
A method of analyzing power noise by the power noise analysis unit 120 based on an assumption that the source voltage Vs of the transistor model MM is equal to the power voltage VDD may be a type of a custom design method.
The power noise analysis unit 120 may generate a node equation with respect to the first node N1, and the voltage vector V may be expressed by Equation 1 below,
V=G^{−1}·U Equation 1
wherein a power network matrix ‘G’ is a result of expressing in the form of a matrix the resistance value of the power network model Rpn included in the power network information PNI, and ‘U’ denotes a vector that changes according to current vector I, and that is a combination of the current vector I and a constant (e.g., the power voltage VDD or the resistance value Rpn). The voltage vector ‘V’ may be calculated using a linear analysis method.
Here consistent with the foregoing definition, power noise may be understood as a voltage drop with respect to a power voltage (e.g., first power voltage VDD) due to the power network 310 with respect to each of the plurality of cells 320. In the working example, power noise is equal to the difference between the first power voltage VDD and the voltage vector V determined by Equation 1.
The power noise analysis unit 120 may generate the power network matrix G from the power network information PNI so as to analyze power noise. Also, the power noise analysis unit 120 may generate or update the current vector I based on the present current information CI.
At a first time t_{0 }of
The power noise analysis unit 120 may calculate a modified voltage vector V′_{0 }from the power network matrix G and the current vector I that are generated beforehand. Here, the modified voltage vector V′_{0 }denotes a voltage vector calculated from a current vector I generated or updated based on the modified current information CI′_{0}, and the voltage vector V_{0 }denotes a voltage vector calculated from a current vector I generated or updated based on the present current information CI_{0}. However, at time t_{0}, the present current information CI_{0 }and the modified current information CI′_{0 }are the same and thus the modified voltage vector V′_{0 }and the voltage vector V_{0 }are the same.
At time t_{1}, the power noise analysis unit 120 may receive new present current information CI_{1}, and generate modified current information CI′_{1 }by modifying the present current information CI_{1 }based on a previous analysis result.
It is assumed that one of drain currents included in the present current information CI_{1 }is drain current I_{D}.
The drain current I_{D }may be expressed by Equation 2 below,
wherein ‘μ_{eff’ }denotes effective surface mobility, ‘Vgs’ denotes a voltage between the gate and the source of the transistor model MM, and ‘C_{ox}’, ‘W/L’, and ‘Vth’ have been described above.
The effective surface mobility μ_{eff }is a value obtained when the lowfield mobility μ_{0 }decreases due to a verticalfield effect. The relationship between the effective surface mobility μ_{eff }and the lowfield mobility μ_{0 }may be expressed by Equation 3 below,
wherein “θ” is an offset.
The drain current I_{D }is based on the present current information CI_{1 }and is thus a drain current generated when a gate voltage and a source voltage of the transistor model MM is equal to the ground voltage VSS and the power voltage VDD, respectively.
The power noise analysis unit 120 may calculate modified drain current I′_{D }which is drain current when the previous analysis result (i.e., a dropped voltage V corresponding to the transistor model MM among modified voltage vectors V′ generated at the point of time t_{0}) is used as the source voltage of the transistor model MM.
That is, the power noise analysis unit 120 may calculate the modified drain current I′_{D }by using Equation 4 below which is derived from Equations 2 and 3,
wherein ‘Vg’ denotes the ground voltage VSS, ‘Vs’ denotes the power voltage VDD, and ‘V'"'"'s’ denotes the previous analysis result.
That is, the previous analysis result V'"'"'s means a voltage of the first node N1 or the source voltage of the transistor model MM when the power network model Rpn exists. Thus, the modified drain current I′_{D }reflecting the previous analysis result is more similar to an actual model than the drain current I′_{D }obtained based on an assumption that the power network model Rpn does not exist (i.e., where Vs=VDD).
Equation 4 may be derived from the ratio between the drain current I_{D }and the modified drain current I′_{D }when the transistor model MM operates in a saturation region.
The power noise analysis unit 120 may generate modified current information CI′_{1 }that includes modified drain current I′_{D }corresponding to each of the plurality of cells 320. The power noise analysis unit 120 may update current vector I based on the modified current information CI′_{1}.
Also, the power noise analysis unit 120 may calculate a modified voltage vector V′_{1}, based on the power network matrix G and the updated current vector I and according to Equation 1.
Each of components of the modified voltage vector V′_{1 }may be less than each of components corresponding to the voltage vector V_{1 }calculated from the current vector I updated based on the present current information CI_{0}. This is because the modified current information CI′_{1 }is not based on an assumption that the source voltage of the transistor model MM is equal to the power voltage VDD, and is calculated from the modified voltage vector V′_{0 }when the power network model Rpn exists at the previous point of time t_{0}.
Similarly, modified voltage vectors V′_{2 }to V′_{n }generated at the subsequent points of time t_{2 }to t_{n}, respectively, are generated from modified voltage vectors V′_{1 }to V′_{n1 }generated at points of time right before the points of time t_{2 }to t_{n}, i.e., a previous analysis result, based on modified current information CI′_{2 }to CI′_{n }obtained by modifying present current information CI_{2 }to CI_{n}. Here, ‘n’ denotes an integer that is equal to or greater than ‘1’ and may be a value set beforehand in the device design program 100.
When the generation of the modified voltage vectors V′_{0 }to V′_{n }is completed, the power noise analysis unit 120 may provide the modified voltage vectors V′_{0 }to V′_{n }as an analysis result AR to the design unit 110.
The design unit 110 may modify the semiconductor device 300 based on the analysis result AR, i.e., analyzed power noise. For example, if a minimum driving voltage for operating the cells 320 normally is 2.0V, the design unit 110 may not modify the semiconductor device 3000 in relation to the cells 320 when a minimum value of a dropped voltage V included in the analysis result AR at the point of time t_{0 }to t_{n }is 2V or more. However, when the minimum value of the dropped voltage V is less than 2.0V, the design unit 110 may modify the structures of the power network 310 and/or the cells 320 of the semiconductor device 300 in relation to the cell 320 so as to secure a minimum driving voltage.
Referring back to
Data may be communicated among the CPU 50, memory 80, and I/O interface 200 via the bus 150 using conventionally understood approaches.
The I/O interface 200 may be used to convert input data received from external circuits (e.g., an externally disposed storage medium, a display, a user input, etc.) as well as output data to be provided to external circuits by the computing device 10.
At this point it should be noted that a device design program according to some embodiments of the inventive concept will not operate under an assumption that the power network model Rpn does not exist, and/or under an assumption that a present analysis is generated to reflect a previous analysis result which is power noise when the power network model Rpn is connected to the transistor model MM, thereby even more accurately analyzing the power noise.
Referring to
The design unit 110 may model the power network model Rpn and the transistor model MM after the semiconductor device 300 (S20).
The power noise analysis unit 120 analyzes power noise in the semiconductor device 300 by generating a present analysis result based on a previous analysis result (S30). In certain embodiments of the inventive concept, the operation S30 of the method summarized in
Thus, with reference to
The power noise analysis unit 120 may generate a power network matrix G which is a result of expressing in the form of a matrix a resistance value of the power network model Rpn included in the power network information PNI (S110).
The power noise analysis unit 120 may generate modified current information CI′ by modifying present current information CI based on the previous analysis result (a modified voltage vector V′ at a previous point of time) (S120). The modified current information CI′ is generated by performing an arithmetic operation on the present current information CI, a source voltage Vs′ of the transistor model MM according to the previous analysis result (the modified voltage vector V′) and the parameters θ and Vth of the transistor model MM, as shown in Equation 4.
The power noise analysis unit 120 may update the current vector I using the modified current information CI′ (S130).
The power noise analysis unit 120 may calculate a present analysis result which is a modified voltage vector V′, based on the power network matrix G and the updated current vector I and according to Equation 1 (S140).
Operations S120 to S140 are repeatedly performed from a point of time t_{0 }to a point of time t_{n }(S150).
When generation of modified voltage vectors V′_{0 }to V′_{n }is completed, the power noise analysis unit 120 may output the modified voltage vectors V′_{0 }to V′_{n }as an analysis result AR to the design unit 110 (S160).
Returning to
In certain embodiments, the inventive concept may be embodied, at least in part, as computerreadable code capable of being stored on at least one computerreadable medium, and further capable of being executed by computational and control logic to execute one or more methods, like the ones described above. The computerreadable recording medium may be any data storage device capable of storing program data and being read by the computing device 10 of
Those skilled in the art are deemed capable of writing, editing and functionally arranging programs, code(s), and code segments to variously implement embodiments of the inventive concept.
In a method of designing a semiconductor device according to embodiments of the inventive concept, it need not be assumed that the power network model Rpn does not exist, and/or that a present analysis result is generated to reflect a previous analysis result representing power noise when the power network model Rpn is connected to the transistor model MM, thereby more actually analyzing power noise.
In a computing device capable of executing a program performing a method of analyzing power noise in a semiconductor device, a semiconductor device designing method including the method, and a program storage medium storing the program according to some embodiments of the inventive concept, it is not assumed that a power network model does not exist, and a present analysis result is generated to reflect a previous analysis result representing power noise when a power network model is connected to a transistor model, thereby more actually analyzing power noise.
While the inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the scope of the following claims.