Independent test partition clock coordination across multiple test partitions
First Claim
1. A chip test system comprising:
- a first test partition operable to perform test operations based upon a first local test clock signal;
a second test partition operable to perform test operations based upon a second local test clock signal, wherein a trigger edge of the first local test clock signal is staggered with respect to a trigger edge of the second local test clock signal, wherein the stagger is coordinated to mitigate power consumption by test operations in the first test partition and test operations in the second test partition, wherein the stagger is also based on respective distance from a power source to the first test partition and second test partition and respective flop counts in the first test partition and second test partition; and
a centralized controller configured to coordinate testing between the plurality of test partitions, wherein the coordination includes managing communication of test information between the plurality of test partitions and external pins.
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Abstract
Granular dynamic test systems and methods facilitate efficient and effective timing of test operations. In one embodiment, a chip test system comprises: a first test partition operable to perform test operations based upon a first local test clock signal; a second test partition operable to perform test operations based upon a second local test clock signal; and a centralized controller configured to coordinate testing between the plurality of test partitions, wherein the coordination includes managing communication of test information between the plurality of test partitions and external pins. In one exemplary implementation, a trigger edge of the first local test clock signal is staggered with respect to a trigger edge of the second local test clock signal, wherein the stagger is coordinated to mitigate power consumption by test operations in the first test partition and test operations in the second test partition.
107 Citations
20 Claims
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1. A chip test system comprising:
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a first test partition operable to perform test operations based upon a first local test clock signal; a second test partition operable to perform test operations based upon a second local test clock signal, wherein a trigger edge of the first local test clock signal is staggered with respect to a trigger edge of the second local test clock signal, wherein the stagger is coordinated to mitigate power consumption by test operations in the first test partition and test operations in the second test partition, wherein the stagger is also based on respective distance from a power source to the first test partition and second test partition and respective flop counts in the first test partition and second test partition; and a centralized controller configured to coordinate testing between the plurality of test partitions, wherein the coordination includes managing communication of test information between the plurality of test partitions and external pins. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of chip testing, the method comprising:
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accessing a first test clock signal associated with a first partition; shifting an edge of the first test clock signal based upon an edge of a second test clock signal associated with a second test partition, wherein the shift is based on respective distance from a power source to the first test partition and second test partition and respective flop counts in the first test partition and second test partition; and performing test operations in the first partition in accordance with the first clock signal. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A chip test system comprising:
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a first test partition configured to execute a first test pattern; a second test partition configured to execute a second test pattern, wherein the first test partition is operable to execute the first test pattern in accordance with a first local test clock signal and the second test partition is operable to execute the second test pattern in accordance with a second local test clock signal, and an adjustment is made in timing of trigger edges associated with the first local test clock with respect to timing of trigger edges associated with the second local test clock, wherein the second test partition comprises; a positive edge counter that counts positive clock edges; a negative edge counter that counts negative clock edges; stagger logic that introduces the adjustment in a clock edge, the stagger logic coupled to the positive edge counter and the negative edge counter; a negative edge divider configured to divide the clock signal based on a negative edge count, the negative edge divider coupled to the stagger logic; a positive edge divider configured to divide the clock signal based on a positive edge count, the positive edge divider coupled to the stagger logic; a decoder configured to control the negative edge divider and positive edge divider, the decoder coupled to the negative edge divider and positive edge divider; and a multiplexer configured to select between an output of the negative edge divider and an output of the positive edge divider, the multiplexer coupled to the negative edge divider, the positive edge divider and the stagger logic; and a centralized controller configured to coordinate testing between the plurality of test partitions, wherein the coordination includes managing communication of test information between the plurality of test partitions and external pins. - View Dependent Claims (18, 19, 20)
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Specification