Reverse-current-prevention circuit and power supply circuit

• US 10,444,777 B2
• Filed: 12/17/2018
• Issued: 10/15/2019
• Est. Priority Date: 01/15/2018
• Status: Active Grant

• Current Assignee: Ablic Inc. (MinebeaMitsumi Inc.)
• Original Assignee: Ablic Inc. (MinebeaMitsumi Inc.)
• Inventors: Tomioka, Tsutomu
• Primary Examiner(s): Laxton, Gary L
• Assistant Examiner(s): Tiku, Sisay G
• Application Number:
  US16/221,770
• Publication Number:
  US 20190220048A1
• Time in Patent Office: 302 Days
• Field of Search: 361 56, 361 77, 361 82, 361 84, 327538-543
• CPC Class Codes: G01R 19/16528 using digital techniques or performing arithmetic operations using digital techniques to measure a voltage or a current, see G01R19/25
• CPC Class Codes: G05F 1/571 with overvoltage detector
• CPC Class Codes: H02H 3/18 responsive to reversal of direct current
• CPC Class Codes: H02H 7/1213 for DC-DC converters
• CPC Class Codes: H03K 17/166 Soft switching
• CPC Class Codes: H03K 17/6871 the output circuit comprising more than one controlled field-effect transistor
• CPC Class Codes: H03K 2217/0054 Gating switches, e.g. pass gates

Abstract

A reverse-current-prevention circuit includes a reverse-current-prevention transistor of a P-channel MOS transistor inserted between an input terminal supplied with a power supply voltage and an output stage transistor of a P-channel MOS transistor providing an output voltage from an output terminal, and a reverse-current-prevention controller configured to turn the reverse-current-prevention transistor from on to off according to exceedance of the output voltage to the power supply voltage. The reverse-current-prevention controller includes a first transistor of a depletion type P-channel MOS transistor having a source and gate respectively connected to the output terminal and the input terminal, and a second transistor of a depletion type P-channel MOS transistor having a source and gate respectively connected to a drain of the first transistor and a gate of the reverse-current-prevention transistor, and a drain grounded.

Claims

1. A reverse-current-prevention circuit comprising:

a reverse-current-prevention transistor being a P-channel MOS transistor inserted in series between an input terminal supplied with a power supply voltage and an output stage transistor being a P-channel MOS transistor suppling a prescribed output voltage from an output terminal; and

a reverse-current-prevention controller configured to bring the reverse-current-prevention transistor from an on state to an off state according to exceedance of the output voltage to the power supply voltage, and having;

a first transistor being a depletion type P-channel MOS transistor and having a source connected to the output terminal and a gate connected to the input terminal, and

a second transistor being a depletion type P-channel MOS transistor and having a source connected to a gate of the second transistor, a drain of the first transistor, and a gate of the reverse-current-prevention transistor, and a drain being grounded,

wherein the reverse-current-prevention controller controls on and off of the reverse-current-prevention transistor according to a voltage of the drain of the first transistor.

2. The reverse-current-prevention circuit according to claim 1, wherein the gates of the first transistor and the second transistor have an equal in aspect ratio, and

wherein the voltage of the drain of the first transistor rises to turn off the reverse-current-prevention transistor according to exceedance of the output voltage applied to the source of the first transistor to the power supply voltage applied to the gate of the first transistor.

3. The reverse-current-prevention circuit according to claim 2, further comprising a PN junction element inserted in a forward direction between the output terminal and the source of the first transistor.

4. The reverse-current-prevention circuit according to claim 2, further comprising a waveform shaping circuit inserted between the drain of the first transistor and the gate of the reverse-current-prevention transistor.

5. The reverse-current-prevention circuit according to claim 2, wherein a third transistor being a depletion type P-channel MOS transistor and a switch are inserted in parallel between the drain of the second transistor and the ground,

wherein the third transistor has a source connected to the drain of the second transistor, a gate connected to the gate of the second transistor, and drain being grounded, and

wherein on and off of the switch is controlled by the reverse-current-prevention controller along with the reverse-current-prevention transistor.

6. The reverse-current-prevention circuit according to claim 1, further comprising a PN junction element inserted in a forward direction between the output terminal and the source of the first transistor.

7. The reverse-current-prevention circuit according to claim 6, further comprising a waveform shaping circuit inserted between the drain of the first transistor and the gate of the reverse-current-prevention transistor.

8. The reverse-current-prevention circuit according to claim 6, wherein a third transistor being a depletion type P-channel MOS transistor and a switch are inserted in parallel between the drain of the second transistor and the ground,

wherein the third transistor has a source connected to the drain of the second transistor, a gate connected to the gate of the second transistor, and drain being grounded, and

wherein on and off of the switch is controlled by the reverse-current-prevention controller along with the reverse-current-prevention transistor.

9. The reverse-current-prevention circuit according to claim 1, further comprising a waveform shaping circuit inserted between the drain of the first transistor and the gate of the reverse-current-prevention transistor.

10. The reverse-current-prevention circuit according to claim 9, wherein a third transistor being a depletion type P-channel MOS transistor and a switch are inserted in parallel between the drain of the second transistor and the ground,

wherein the third transistor has a source connected to the drain of the second transistor, a gate connected to the gate of the second transistor, and drain being grounded, and

wherein on and off of the switch is controlled by the reverse-current-prevention controller along with the reverse-current-prevention transistor.

11. The reverse-current-prevention circuit according to claim 1, further comprising:

a resistor inserted between the drain and gate of the reverse-current-prevention transistor, and

a current controller inserted between the gate of the reverse-current-prevention transistor and the drain of the first transistor and configured to control a current flow through the resistor by the voltage of the drain of the first transistor,

wherein the current controller increases the current flow through the resistor according to exceedance of the output voltage to the power supply voltage.

12. The reverse-current-prevention circuit according to claim 11, wherein a third transistor being a depletion type P-channel MOS transistor and a switch are inserted in parallel between the drain of the second transistor and the ground,

wherein the third transistor has a source connected to the drain of the second transistor, a gate connected to the gate of the second transistor, and drain being grounded, and

wherein on and off of the switch is controlled by the reverse-current-prevention controller along with the reverse-current-prevention transistor.

13. The reverse-current-prevention circuit according to claim 1, wherein a third transistor being a depletion type P-channel MOS transistor and a switch are inserted in parallel between the drain of the second transistor and the ground,

wherein the third transistor has a source connected to the drain of the second transistor, a gate connected to the gate of the second transistor, and drain being grounded, and

wherein on and off of the switch is controlled by the reverse-current-prevention controller along with the reverse-current-prevention transistor.

14. A power supply circuit comprising:

an output stage transistor being a P-channel MOS transistor and having a source supplied with a power supply voltage from an input terminal and a drain from which a prescribed output voltage is provided to an output terminal in accordance with a gate voltage applied to a gate of the output stage transistor;

a reverse-current-prevention transistor being a P-channel MOS transistor and having a source connected to the input terminal and a drain connected to the source of the output stage transistor, and configured to prevent a reverse current coming from the output terminal through a parasitic diode on the source side of the output stage transistor; and

a reverse-current-prevention controller configured to bring the reverse-current-prevention transistor from an on state to an off state according to exceedance of the output voltage to the power supply voltage,

and having;

a first transistor being a depletion type P-channel MOS transistor and having a source connected to the output terminal and a gate connected to the input terminal, and

a second transistor being a depletion type P-channel MOS transistor and having a source connected to a gate of the second transistor, a drain of the first transistor, and a gate of the reverse-current-prevention transistor, and a drain being grounded.