Memory system for dualizing first memory based on operation mode

• US 10,445,003 B2
• Filed: 10/11/2016
• Issued: 10/15/2019
• Est. Priority Date: 10/15/2015
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Kim, Min-Chang, Kim, Chang-Hyun, Lee, Do-Yun, Lee, Yong-Woo, Lee, Jae-Jin, Jung, Hoe-Kwon
• Primary Examiner(s): Mackall, Larry T
• Application Number:
  US15/290,824
• Publication Number:
  US 20170109060A1
• Time in Patent Office: 1,099 Days
• CPC Class Codes: G06F 12/0895 of parts of caches, e.g. directory or tag array
• CPC Class Codes: G06F 13/4286 using a handshaking protocol, e.g. RS232C link
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0634 by changing the state or mode of one or more devices
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices.

Claims

1. A memory system comprising:

a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data;

a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and

a processor suitable for executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices,

wherein the first and second memories are separated from the processor,

wherein the processor accesses the second memory device through the first memory device,

wherein the first memory controller transfers a signal between the processor and the second memory device based on at least one of values of a memory selection field and a handshaking information field included in the signal,

wherein the first memory includes a high-capacity memory, which has a lower latency than the second memory and operates as a cache memory for the second memory, and a high-speed memory, which has a lower latency than the high-capacity memory and operates as a cache memory for the high-capacity memory,

wherein the first memory controller includes a high-capacity memory cache controller suitable for controlling the high-capacity memory to store data, and a high-speed memory cache controller suitable for controlling the high-speed memory to store data,

wherein the processor and the second memory device communicate with each other through an input/output bus,

wherein the processor, the high-speed memory cache controller and the high-speed memory communicate with each other through a first input/output bus, which is a part of the input/output bus, in a high-speed operation mode,

wherein the processor, the high-capacity memory cache controller and the high-capacity memory communicate with each other through a second input/output bus, which is another part of the input/output bus, in a high-capacity operation mode,

wherein the high-capacity memory caches data of the second memory through the second input/output bus under a control of the second memory controller and the high-capacity memory cache controller during the high-speed operation mode,

wherein the high-speed memory includes a plurality of high-capacity memory cores, and

wherein the high-speed memory further includes a high-speed operation memory logic operatively and commonly coupled with the plurality of high-capacity memory cores, and suitable for supporting high-speed data communication between the processor and the plurality of high-capacity memory cores.

2. The memory system of claim 1,

wherein the first memory devices maintains latency information of the high-speed memory and the high-capacity memory, and the second memory device maintains latency information of the second memory, and

wherein the processor separately communicates with each of the high-speed memory, the high-capacity memory, and the second memory according to the latency information respectively provided from the first memory device and the second memory devices.

3. The memory system of claim 1, wherein the value of the memory selection field indicates one of the first and second memory devices as a destination of the signal.

4. The memory system of claim 1, wherein the value of the memory selection field indicates one of the high-speed memory, the high-capacity memory, and the second memory as a destination of the signal.

5. The memory system of claim 1, wherein the value of the memory selection field indicates two or more among the processor and the first and second memory devices as a source and a destination of the signal.

6. The memory system of claim 1, wherein the value of the memory selection field indicates two or more among the processor and the high-speed memory, the high-capacity memory, and the second memory as a source and a destination of the signal.

7. The memory system of claim 1, wherein the value of the handshaking information field indicates the signal as one of a data request signal from the processor to the second memory, a data ready signal from the second memory to the processor and a session start signal from the processor to the second memory.

8. The memory system of claim 1, wherein the first memory device is a volatile memory device.

9. The memory system of claim 1, wherein the second memory device is a nonvolatile memory device.

10. The memory system of claim 1, wherein the first memory controller further includes a router suitable for routing the signal transferred from the processor and the second memory device based on the at least one of values of the memory selection field and the handshaking information field included in the signal thereby:

allowing the processor, the high-speed memory cache controller and the high-speed memory to perform the memory operation through the first input/out bus,

allowing the processor, the high-capacity memory cache controller and the high-capacity memory to perform the memory operation through the second input/output bus, and

allowing the processor, the second memory controller and the second memory to perform the memory operation through the input/output bus.

11. A memory system comprising:

a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data;

a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and

a processor suitable for accessing the first memory, and accessing the second memory through the first memory device,

wherein the first memory controller transfers a signal between the processor and the second memory device based on at least one of values of a memory selection field and a handshaking information field included in the signal,

wherein the first memory includes a high-capacity memory, which has a lower latency than the second memory and operates as a cache memory for the second memory, and a high-speed memory, which has a lower latency than the high-capacity memory and operates as a cache memory for the high-capacity memory,

wherein the first memory controller includes a high-capacity memory cache controller suitable for controlling the high-capacity memory to store data, and a high-speed memory cache controller suitable for controlling the high-speed memory to store data, and

wherein the processor and the second memory device communicate with each other through an input/output bus,

wherein the processor, the high-speed memory cache controller and the high-speed memory communicate with each other through a first input/output bus, which is a part of the input/output bus, in a high-speed operation mode,

wherein the processor, the high-capacity memory cache controller and the high-capacity memory communicate with each other through a second input/output bus, which is another part of the input/output bus, in a high-capacity operation mode, and

wherein the high-capacity memory caches data of the second memory through the second input/output bus under a control of the second memory controller and the high-capacity memory cache controller during the high-speed operation mode,

wherein the high-speed memory includes a plurality of high-capacity memory cores, and

wherein the high-speed memory further includes a high-speed operation memory logic operatively and commonly coupled with the plurality of high-capacity memory cores, and suitable for supporting high-speed data communication between the processor and the plurality of high-capacity memory cores.

12. The memory system of claim 11,

wherein the first memory device maintains latency information of the high-speed memory and the high-capacity memory, and the second memory device maintains latency information of the second memory, and

wherein the processor separately communicates with each of the high-speed memory, the high-capacity memory, and the second memory according to the latency information respectively provided from the first memory device and the second memory device.

13. The memory system of claim 11, wherein the value of the memory selection field indicates one of the first and second memory devices as a destination of the signal.

14. The memory system of claim 11, wherein the value of the memory selection field indicates one of the high-speed memory, the high-capacity memory, and the second memory as a destination of the signal.

15. The memory system of claim 11, wherein the value of the memory selection field indicates two or more among the processor and the first and second memory devices as a source and a destination of the signal.

16. The memory system of claim 11, wherein the value of the memory selection field indicates two or more among the processor and the high-speed memory, the high-capacity memory, and the second memory as a source and a destination of the signal.

17. The memory system of claim 11, wherein the value of the handshaking information field indicates the signal as one of a data request signal from the processor to the second memory, a data ready signal from the second memory to the processor and a session start signal from the processor to the second memory.

18. The memory system of claim 11, wherein the first memory device is volatile memory device.

19. The memory system of claim 11, wherein the second memory device is a nonvolatile memory device.

20. The memory system of claim 11, wherein the first memory controller further includes a router suitable for routing the signal transferred from the processor and the second memory device based on the at least one of values of the memory selection field and the handshaking information field included in the signal thereby:

allowing the processor, the high-speed memory cache controller and the high-speed memory to perform the memory operation through the first input/out bus,

allowing the processor, the high-capacity memory cache controller and the high-capacity memory to perform the memory operation through the second input/output bus, and

allowing the processor, the second memory controller and the second memory to perform the memory operation through the input/output bus.